Winner-take-all circuit using CMOS technology
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Data
1999-01-01
Autores
Oki, N.
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IEEE Computer Soc
Resumo
In this paper is presented an implementation of winner-take-all circuit using CMOS technology. In the proposed configuration the inputs are current and the outputs voltage. The simulation results show that the circuit can be a winner if its input is larger than the other by 2 mu A. The simulation also shows that the response time is 100ns at a 0.2pF load capacitance. To demonstrate the functionality of the proposed circuit, a two-input winner take all circuit was built and tested by using discrete CMOS transistor array (CD40071).
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1998 Midwest Symposium on Circuits and Systems, Proceedings. Los Alamitos: IEEE Computer Soc, p. 568-570, 1999.