Low voltage four-quadrant current multiplier: An improved topology for n-well CMOS process
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Data
2007-01-01
Autores
Oliveira, Vlademir J. S. [UNESP]
Oki, Nobuo [UNESP]
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IEEE
Resumo
An analog CMOS current multiplier building block for low voltage applications using an n-well process is presented. The multiplier equations are derived to proof its linear characteristic, and then a low voltage design is proposed. Post layout simulation in a 0.35 mu m AMS CMOS process and 1.5V supply voltage shows a THD of 0.84% at 10 MHz and a frequency response bandwidth of 140 MHz.
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2007 International Conference on Design & Technology of Integrated Systems In Nanoscale Era. New York: IEEE, p. 52-55, 2007.