An algorithmic of analog-to-digital converter using current-mode and digital CMOS process
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Data
1999-01-01
Autores
Oki, N.
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IEEE Computer Soc
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In this paper a new algorithmic of Analog-to-Digital Converter is presented. This new topology use the current-mode technique that allows a large dynamic range and can be implemented in digital CMOS process. The ADC proposed is very small and can handle high sampling rates. Simulation results using a 1.2um CMOS process show that an 8-b ADC can support a sampling rate of 50MHz.
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1998 Midwest Symposium on Circuits and Systems, Proceedings. Los Alamitos: IEEE Computer Soc, p. 520-521, 1999.