A transactional runtime system for the Cell/BE architecture

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dc.contributor.authorBaldassin, Alexandro José [UNESP]
dc.contributor.authorGoldstein, Felipe
dc.contributor.authorAzevedo, Rodolfo
dc.contributor.institutionUniversidade Estadual Paulista (Unesp)
dc.contributor.institutionUniversidade Estadual de Campinas (UNICAMP)
dc.date.accessioned2014-05-20T15:33:24Z
dc.date.available2014-05-20T15:33:24Z
dc.date.issued2012-12-01
dc.description.abstractSingle-core architectures have hit the end of the road and industry and academia are currently exploiting new multicore design alternatives. In special, heterogeneous multicore architectures have attracted a lot of attention but developing applications for such architectures is not an easy task due to the lack of appropriate tools and programming models. We present the design of a runtime system for the Cell/BE architecture that works with memory transactions. Transactional programs are automatically instrumented by the compiler, shortening development time and avoiding synchronization mistakes usually present in lock-based approaches (such as deadlock). Experimental results conducted with a prototype implementation and the STAMP benchmark show good scalability for applications with moderate to low contention levels, and whose transactions are not too small. For those cases in which a small performance loss is admissible, we believe that the ease of programming provided by transactions greatly pays off. (C) 2012 Elsevier B.V. All rights reserved.en
dc.description.affiliationUniv Estadual Paulista, UNESP, Rio Claro, Brazil
dc.description.affiliationUniv Estadual Campinas, UNICAMP, Campinas, SP, Brazil
dc.description.affiliationUnespUniv Estadual Paulista, UNESP, Rio Claro, Brazil
dc.description.sponsorshipIBM
dc.description.sponsorshipConselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)
dc.description.sponsorshipFundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)
dc.description.sponsorshipIdFAPESP: 11/19373-6
dc.format.extent1535-1546
dc.identifierhttp://dx.doi.org/10.1016/j.jpdc.2012.08.001
dc.identifier.citationJournal of Parallel and Distributed Computing. San Diego: Academic Press Inc. Elsevier B.V., v. 72, n. 12, p. 1535-1546, 2012.
dc.identifier.doi10.1016/j.jpdc.2012.08.001
dc.identifier.issn0743-7315
dc.identifier.urihttp://hdl.handle.net/11449/42030
dc.identifier.wosWOS:000310669600001
dc.language.isoeng
dc.publisherAcademic Press Inc. Elsevier B.V.
dc.relation.ispartofJournal of Parallel and Distributed Computing
dc.relation.ispartofjcr1.815
dc.relation.ispartofsjr0,502
dc.rights.accessRightsAcesso restrito
dc.sourceWeb of Science
dc.subjectMultiprocessorsen
dc.subjectParallel programmingen
dc.subjectTransactional memoryen
dc.titleA transactional runtime system for the Cell/BE architectureen
dc.typeArtigo
dcterms.licensehttp://www.elsevier.com/about/open-access/open-access-policies/article-posting-policy
dcterms.rightsHolderAcademic Press Inc. Elsevier B.V.
unesp.author.lattes4738829911864396[1]
unesp.author.orcid0000-0001-8824-3055[1]
unesp.campusUniversidade Estadual Paulista (Unesp), Instituto de Geociências e Ciências Exatas, Rio Claropt

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Artigos - Estatistica, Matemática Aplicada e Computação - IGCE