Publicação: Performance evaluation of Tunnel-FET basic amplifier circuits
dc.contributor.author | Rangel, R. S. | |
dc.contributor.author | Agopian, P. G. D. [UNESP] | |
dc.contributor.author | Martino, J. A. | |
dc.contributor.author | Murphy, R. S. | |
dc.contributor.institution | Universidade de São Paulo (USP) | |
dc.contributor.institution | CI Brasil Program CT SP | |
dc.contributor.institution | Universidade Estadual Paulista (Unesp) | |
dc.date.accessioned | 2019-10-04T12:14:12Z | |
dc.date.available | 2019-10-04T12:14:12Z | |
dc.date.issued | 2019-01-01 | |
dc.description.abstract | This work analyzes the performance of measured Tunneling Field-Effect Transistors (TFET) when applied to analog circuits. The method uses a look-up table based behavioral model, taking the experimental results from a fabricated silicon pTFET as input. The Verilog-A behavioral language is used to implement the TFET model, enabling the use with spice-like simulators along with passive and active elements, achieving bigger circuits than other implementations involving numerical multiphysics simulation of the device. The model is further incremented with device capacitances, and the response of analog circuits is considered. An Operational Transconductance Amplifier (OTA) is presented, showing near 130 dB open-loop gain and 18.9nW power consumption. | en |
dc.description.affiliation | Univ Sao Paulo, LSI PSI USP, Sao Paulo, Brazil | |
dc.description.affiliation | CI Brasil Program CT SP, Sao Paulo, Brazil | |
dc.description.affiliation | Sao Paulo State Univ UNESP, Sao Joao Da Boa Vista, Brazil | |
dc.description.affiliationUnesp | Sao Paulo State Univ UNESP, Sao Joao Da Boa Vista, Brazil | |
dc.description.sponsorship | Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) | |
dc.description.sponsorship | Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) | |
dc.format.extent | 21-24 | |
dc.identifier.citation | 2019 Ieee 10th Latin American Symposium On Circuits & Systems (lascas). New York: Ieee, p. 21-24, 2019. | |
dc.identifier.issn | 2330-9954 | |
dc.identifier.lattes | 0496909595465696 | |
dc.identifier.orcid | 0000-0002-0886-7798 | |
dc.identifier.uri | http://hdl.handle.net/11449/184507 | |
dc.identifier.wos | WOS:000469514000006 | |
dc.language.iso | eng | |
dc.publisher | Ieee | |
dc.relation.ispartof | 2019 Ieee 10th Latin American Symposium On Circuits & Systems (lascas) | |
dc.rights.accessRights | Acesso aberto | pt |
dc.source | Web of Science | |
dc.subject | TFET | |
dc.subject | Circuit Simulation | |
dc.subject | Verilog-A | |
dc.title | Performance evaluation of Tunnel-FET basic amplifier circuits | en |
dc.type | Trabalho apresentado em evento | pt |
dcterms.license | http://www.ieee.org/publications_standards/publications/rights/rights_policies.html | |
dcterms.rightsHolder | Ieee | |
dspace.entity.type | Publication | |
unesp.author.lattes | 0496909595465696[2] | |
unesp.author.orcid | 0000-0002-0886-7798[2] | |
unesp.campus | Universidade Estadual Paulista (UNESP), Faculdade de Engenharia, São João da Boa Vista | pt |