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Parasitic conduction on Ω-gate nanowires SOI nMOSFETs

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dc.contributor.authorSilva, V. C.P.
dc.contributor.authorMartino, J. A.
dc.contributor.authorAgopian, P. G.D. [UNESP]
dc.contributor.institutionUniversidade de São Paulo (USP)
dc.contributor.institutionUniversidade Estadual Paulista (Unesp)
dc.date.accessioned2018-12-11T16:54:28Z
dc.date.available2018-12-11T16:54:28Z
dc.date.issued2018-01-01
dc.description.abstractIn this work is analyzed the influence of fixed charges and interface traps on the subthreshold region of O-Gate Nanowires SOI nMOSFETs devices with different channel width (Wfin) and length (L). The implementation of the fixed charges on the back interface (channel/buried oxide) results in a parasitic conduction in this region, reducing the effective threshold voltage of the transistor. It was verified that the presence of these fixed charges and of the interface traps hardly affect the subthreshold swing due to the strong coupling among the interfaces.en
dc.description.affiliationLSI/PSI/USP University of Sao Paulo
dc.description.affiliationSao Paulo State University (UNESP)
dc.description.affiliationUnespSao Paulo State University (UNESP)
dc.format.extent103-109
dc.identifierhttp://dx.doi.org/10.1149/08508.0103ecst
dc.identifier.citationECS Transactions, v. 85, n. 8, p. 103-109, 2018.
dc.identifier.doi10.1149/08508.0103ecst
dc.identifier.file2-s2.0-85050073901.pdf
dc.identifier.issn1938-5862
dc.identifier.issn1938-6737
dc.identifier.lattes0496909595465696
dc.identifier.orcid0000-0002-0886-7798
dc.identifier.scopus2-s2.0-85050073901
dc.identifier.urihttp://hdl.handle.net/11449/171223
dc.language.isoeng
dc.relation.ispartofECS Transactions
dc.relation.ispartofsjr0,225
dc.relation.ispartofsjr0,225
dc.rights.accessRightsAcesso aberto
dc.sourceScopus
dc.titleParasitic conduction on Ω-gate nanowires SOI nMOSFETsen
dc.typeTrabalho apresentado em evento
dspace.entity.typePublication
unesp.author.lattes0496909595465696[3]
unesp.author.orcid0000-0002-0886-7798[3]

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