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Publicação:
CNOT Gate Mappings to Clifford+T Circuits in IBM Architectures

dc.contributor.authorDe Almeida, Alexandre A. A. [UNESP]
dc.contributor.authorDueck, Gerhard W.
dc.contributor.authorDa Silva, Alexandre C. R. [UNESP]
dc.contributor.institutionUniversidade Estadual Paulista (Unesp)
dc.contributor.institutionUniversity of New Brunswick
dc.date.accessioned2019-10-06T15:49:57Z
dc.date.available2019-10-06T15:49:57Z
dc.date.issued2019-05-01
dc.description.abstractIBM architectures impose some restrictions the quantum circuits that can be implemented. Only gates from Clifford+T gate library can be used and not all of the CNOT gates are available. Some of the CNOT need to be mapped into a sequence of gates. In this paper we present a set of mappings to conform to the restrictions imposed by IBM's architectures. These mappings require fewer gates than SWAP gates. It is well known, that permuting the qubits will yield circuits with different number of gates. The design in this paper uses efficient mappings with qubit permutations to obtain circuits with a reduced number of gates. Results have shown that the proposed approach reduces circuits by up to 64% compared with Qiskit and up to 42% compared with another mapping algorithm.en
dc.description.affiliationSchool of Engineering Ilha Solteira São Paulo State University (Unesp)
dc.description.affiliationFaculty of Computer Science University of New Brunswick
dc.description.affiliationUnespSchool of Engineering Ilha Solteira São Paulo State University (Unesp)
dc.format.extent7-12
dc.identifierhttp://dx.doi.org/10.1109/ISMVL.2019.00010
dc.identifier.citationProceedings of The International Symposium on Multiple-Valued Logic, v. 2019-May, p. 7-12.
dc.identifier.doi10.1109/ISMVL.2019.00010
dc.identifier.issn0195-623X
dc.identifier.scopus2-s2.0-85069157971
dc.identifier.urihttp://hdl.handle.net/11449/187875
dc.language.isoeng
dc.relation.ispartofProceedings of The International Symposium on Multiple-Valued Logic
dc.rights.accessRightsAcesso abertopt
dc.sourceScopus
dc.subjectClifford+T circuits
dc.subjectCNOT mapping
dc.subjectIBM architectures
dc.titleCNOT Gate Mappings to Clifford+T Circuits in IBM Architecturesen
dc.typeTrabalho apresentado em eventopt
dspace.entity.typePublication
unesp.author.lattes7360563327585400[3]
unesp.author.orcid0000-0003-3646-7801[3]
unesp.campusUniversidade Estadual Paulista (UNESP), Faculdade de Engenharia, Ilha Solteirapt

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