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Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications

dc.contributor.authorSilva, V. C.P. [UNESP]
dc.contributor.authorMartino, J. A.
dc.contributor.authorSimoen, E.
dc.contributor.authorVeloso, A.
dc.contributor.authorAgopian, P. G.D. [UNESP]
dc.contributor.institutionUniversidade Estadual Paulista (UNESP)
dc.contributor.institutionUniversidade de São Paulo (USP)
dc.contributor.institutionimec
dc.date.accessioned2025-04-29T20:10:03Z
dc.date.issued2023-10-01
dc.description.abstractThis work presents an experimental evaluation of n-type, gate-all-around (GAA), vertically stacked nanosheet field effect transistors (NSFETs) operating in a temperature (T) range from 473 K down to 173 K and focusing on their use for analog applications. Devices with gate lengths (Lgate) of 28 nm to 200 nm were analyzed. Besides exhibiting a slight short channel effect, the shorter transistors show a good performance in terms of analog application, presenting at 173 K an intrinsic voltage gain (AV) of 30 dB and unit gain frequency (fT) of 185 GHz. This is also seen in two figures of merit that characterize the transistor performance for analog circuit design: the transistor efficiency (gm/IDS) and the gain frequency product (AV*fT). The optimum region of operation was demonstrated to be at strong inversion by the trade-off between gm/IDS and fT, where in this region Lgate = 28 nm presents a gain frequency product of ∼ 5,5THz at T = 173 K. At lower temperature, as expected, it is confirmed that the carrier mobility and the subthreshold swing (SS) improve while the threshold voltage (VT) increases.en
dc.description.affiliationUNESP Sao Paulo State University
dc.description.affiliationLSI/PSI/USP University of Sao Paulo
dc.description.affiliationimec
dc.description.affiliationUnespUNESP Sao Paulo State University
dc.identifierhttp://dx.doi.org/10.1016/j.sse.2023.108729
dc.identifier.citationSolid-State Electronics, v. 208.
dc.identifier.doi10.1016/j.sse.2023.108729
dc.identifier.issn0038-1101
dc.identifier.scopus2-s2.0-85166735870
dc.identifier.urihttps://hdl.handle.net/11449/307667
dc.language.isoeng
dc.relation.ispartofSolid-State Electronics
dc.sourceScopus
dc.subjectAnalog operation
dc.subjectHigh-temperature
dc.subjectLow-temperature
dc.subjectMOSFET
dc.subjectNanosheets (NS)
dc.titleEvaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applicationsen
dc.typeArtigopt
dspace.entity.typePublication
unesp.author.orcid0000-0001-6824-5627[1]
unesp.author.orcid0000-0001-8121-6513[2]
unesp.author.orcid0000-0002-5218-4046[3]
unesp.author.orcid0000-0002-0886-7798[5]

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