An FPGA based 3.8 Tbps Data Sourcing and Emulator System
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Data
2018-02-23
Autores
Ramalho, Lucas Arruda
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Universidade Estadual Paulista (Unesp)
Resumo
A evolução dos Multi Gigabit Transceivers (MGT) nos Field Programmable Gate Arrays (FPGA) trouxeram oportunidades para o desenvolvimento de sistemas de aquisição e formatadores de dados em diversas áreas. As novas famílias de FPGAs são capazes de lidar com canais de transmissão com velocidade da ordem de Gbps que utilizam protocolos seriais de alta velocidade, podendo assim se tornar o futuro dos processadores downstream ou upstream. Os sistemas digitais criados para esse propósito, precisam ser confiáveis e síncronos entre dezenas de canais e placas. Como forma de permitir o teste de projetos com essa taxa massiva de bits, essa tese descreve o desenvolvimento do Data Sourcing System (DSS). Esse sistema deve ser capaz de testar qualquer application upstream ou downstream, permitir controle e acesso remoto aos sinais internos dos FPGAs, medir sincronismo e latência entre MGTs e avaliar integridade de links através de bit error rate (BER). Este trabalho faz parte de uma colaboração internacional liderada pelo Fermilab que propôs, com a contribuição do sistema descrito nesta tese, um sistema de trigger de nível 1 para o Compact Muon Solenoid (CMS) Outer Tracker. O dectetor CMS é um experimento vinculado ao European Organization for Nuclear Research (CERN). O DSS foi implementado sobre a placa Pulsar 2b, uma placa padrão Advanced Telecommunication Computing Architecture (ATCA), desenvolvida pelo Fermilab, que conta com um dispositivo FPGA para programação e costumização de aplicações. O setup de hardware utilizado foi construído sobre dois bastidores ATCA com 12 placas Pulsares 2b em cada. A taxa de dados máxima atingida foi de 3.84 Tbps entre os dois bastidores ATCAs. O DSS está operacional e foi utilizado para emular o fluxo de dados de saída do CMS Silicon Outer Tracker, e auxiliar na demonstração da proposta trigger de nível 1. Esta tese descreve essa demonstração como estudo de caso, que testa o formatador de dados do trigger (downstream) através do DSS e- mulando a saída de dados do detector. Nesse estudo de caso, tanto o DSS e o trigger proposto foram implementados utilizando o mesmo hardware ATCA e a Pulsar 2b. O foco do estudo de caso é descrever a comunicação entre o Data Sourcing shelf e o Pattern Recognition shelf. O DSS atendeu aos requisitos da demonstração provendo uma interface de usuário que permite aos desenvolvedores de trigger inserir sinais de controle e executar operações de leitura e escrita de forma remota nos FPGAs.
The evolution of Fiel Programmable Gate Array (FPGA) Multi Gigabit Transceivers (MGT) brought opportunities for data formatter and data acquisition projects in several areas. The newer FPGA families are capable of handling Gigabits per second (Gbps) I/Os implemented using high speed serial link protocols and to become the future downstream processors. The digital systems created for that purpose need to be reliable and synchronous between dozens of channels and boards. To allow the test of such massive bitrate projects, this work implemented the Data Sourcing System (DSS) e- mulator that is able to produce synchronized data in 12 boards, 480 channels, delivering up to 8 Gbps for each of them. This work is part of a international collaboration, led by Fermilab, that proposed with the contribuition of the system described in this thesis, a Level 1 (L1) tri- gger for the Compact Muon Solenoid (CMS) Outer Tracker. The CMS detector is an European Organization for Nuclear Research (CERN) experiment. The DSS is based on the Pulsar 2b, a custom Advanced Telecommunication Computing Architecture (ATCA) standard FPGA-based board designed by Fermilab to be a scalable high speed link processor system. This hardware setup was implemented at Fermilab using two interconnected ATCA shelves with 12 Pulsar 2b on both. The results show that the system is able to provide data at 3.8 Terabits per second (Tbps), and to measure synchronization, latency and bit error rate of the MGTs. The system is operational and was already used to emulate the CMS Silicon Tracker data, and helped the demonstration of a L1 Trigger approach. This thesis describes the demonstration performed as case of study, which used the DSS as upstream system and tested the trigger data delivery as a downstream. In the case of study, both DSS and the proposed trigger are performed by the same ATCA hardware and the Pulsar 2b. The case of study focused to describe the communication between the Data Sourcing shelf and the Pattern Recognition shelf. Data Sourcing reached those requirements for the demonstration and provided a user interface that allows the trigger developers to insert control signals or to perform W/R operations inside Pulsar 2b FPGA block memories.
The evolution of Fiel Programmable Gate Array (FPGA) Multi Gigabit Transceivers (MGT) brought opportunities for data formatter and data acquisition projects in several areas. The newer FPGA families are capable of handling Gigabits per second (Gbps) I/Os implemented using high speed serial link protocols and to become the future downstream processors. The digital systems created for that purpose need to be reliable and synchronous between dozens of channels and boards. To allow the test of such massive bitrate projects, this work implemented the Data Sourcing System (DSS) e- mulator that is able to produce synchronized data in 12 boards, 480 channels, delivering up to 8 Gbps for each of them. This work is part of a international collaboration, led by Fermilab, that proposed with the contribuition of the system described in this thesis, a Level 1 (L1) tri- gger for the Compact Muon Solenoid (CMS) Outer Tracker. The CMS detector is an European Organization for Nuclear Research (CERN) experiment. The DSS is based on the Pulsar 2b, a custom Advanced Telecommunication Computing Architecture (ATCA) standard FPGA-based board designed by Fermilab to be a scalable high speed link processor system. This hardware setup was implemented at Fermilab using two interconnected ATCA shelves with 12 Pulsar 2b on both. The results show that the system is able to provide data at 3.8 Terabits per second (Tbps), and to measure synchronization, latency and bit error rate of the MGTs. The system is operational and was already used to emulate the CMS Silicon Tracker data, and helped the demonstration of a L1 Trigger approach. This thesis describes the demonstration performed as case of study, which used the DSS as upstream system and tested the trigger data delivery as a downstream. In the case of study, both DSS and the proposed trigger are performed by the same ATCA hardware and the Pulsar 2b. The case of study focused to describe the communication between the Data Sourcing shelf and the Pattern Recognition shelf. Data Sourcing reached those requirements for the demonstration and provided a user interface that allows the trigger developers to insert control signals or to perform W/R operations inside Pulsar 2b FPGA block memories.
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LHC, CMS, Outer Tracker, ATCA, FPGA, High Speed Serial Link Protocol, Data Processing, Trigger concepts and systems, Detector control systems, Control and monitor systems online, Protocolos Seriais de Alta Velocidade, Processamento de dados, Conceitos e sistemas de Trigger, Sistema de controle de detector, Sistemas de controle e monitoramento online