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dc.contributor.authorRangel, R. S.
dc.contributor.authorAgopian, P. G. D. [UNESP]
dc.contributor.authorMartino, J. A.
dc.contributor.authorMurphy, R. S.
dc.identifier.citation2019 Ieee 10th Latin American Symposium On Circuits & Systems (lascas). New York: Ieee, p. 21-24, 2019.
dc.description.abstractThis work analyzes the performance of measured Tunneling Field-Effect Transistors (TFET) when applied to analog circuits. The method uses a look-up table based behavioral model, taking the experimental results from a fabricated silicon pTFET as input. The Verilog-A behavioral language is used to implement the TFET model, enabling the use with spice-like simulators along with passive and active elements, achieving bigger circuits than other implementations involving numerical multiphysics simulation of the device. The model is further incremented with device capacitances, and the response of analog circuits is considered. An Operational Transconductance Amplifier (OTA) is presented, showing near 130 dB open-loop gain and 18.9nW power consumption.en
dc.description.sponsorshipFundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)
dc.description.sponsorshipConselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)
dc.relation.ispartof2019 Ieee 10th Latin American Symposium On Circuits & Systems (lascas)
dc.sourceWeb of Science
dc.subjectCircuit Simulation
dc.titlePerformance evaluation of Tunnel-FET basic amplifier circuitsen
dc.typeTrabalho apresentado em evento
dc.contributor.institutionUniversidade de São Paulo (USP)
dc.contributor.institutionCI Brasil Program CT SP
dc.contributor.institutionUniversidade Estadual Paulista (UNESP)
dc.description.affiliationUniv Sao Paulo, LSI PSI USP, Sao Paulo, Brazil
dc.description.affiliationCI Brasil Program CT SP, Sao Paulo, Brazil
dc.description.affiliationSao Paulo State Univ UNESP, Sao Joao Da Boa Vista, Brazil
dc.description.affiliationUnespSao Paulo State Univ UNESP, Sao Joao Da Boa Vista, Brazil
dc.rights.accessRightsAcesso aberto
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