A Tunnel-FET device model based on Verilog-A applied to circuit simulation

This work proposes a simple methodology for using Tunnel-FET devices, which do not have any accurate first order analytic models, for allowing the integrated circuit simulation with these devices. The method uses experimental characterization to collect the transfers and output characteristics of a new device accessed by Verilog-A models using lookup table method and spline interpolation to simulate the behavior of the real device when in presence of arbitrary biasing. In this paper it is studied a silicon Tunnel-FET (TFET), but it is also valid for any other new semiconductor devices like nanowire and nanosheet. The proposed model allows to anticipate the behavior of complex circuits, whose study would be possible only after the device technology consolidation. Different than compact models, like spice, obtained from physical semiconductor simulators, the proposed Verilog-A models do not need to pass by the physical modeling step, having the advantage of keeping the original device experimental response. The proposed method is validated comparing the current response of the simulated pTFET with experimental data, and with a pTFET current mirror, whose behavior is known from previous works. Further, a pTFET and nTFET complementary common-source amplifier circuit is also analyzed. The response of the analyzed current mirror showed a very stable current output for a large range of load voltage variation inside saturation-like operation region. The analyzed intrinsic gain response of the transistor showed values near to 60 dB, due to its very high Early voltage of pTFET. The voltage gain value also could be analyzed in the common-source circuit, showing a value of 55 dB.