Intrinsic voltage gain of stacked GAA nanosheet MOSFETs operating at high temperatures

Perina, Welder Fernandes; Silva, Vanessa Cristina Pereira; Martino, Joao Antonio; Agopian, Paula Ghedini Der [UNESP]; Simoen, Eddy; Veloso, Anabela

Intrinsic voltage gain of stacked GAA nanosheet MOSFETs operating at high temperatures

Data

2020-04-01

Autores

Perina, Welder Fernandes

Silva, Vanessa Cristina Pereira

Martino, Joao Antonio

Agopian, Paula Ghedini Der

Simoen, Eddy

Veloso, Anabela

Tipo

Trabalho apresentado em evento

Resumo

In this work, the GAA silicon nanosheet MOSFETs basic parameters are evaluated for different channel lengths at high temperatures. The devices showed a subthreshold swing near the theoretical limit, low temperature variation on threshold voltage (dVTH/dT = -0.4 mV/°C) and low drain induced barrier lowering (DIBL = 50 mV/V at 200°C), both for n-type device. The devices achieved an intrinsic voltage gain around 33 dB for the worst case (channel length of 28 nm), showing that this device is a promising technology for the 7 nm node of the MOS roadmap.