Experimental Analysis of Differential Pairs Designed with Line Tunnel FET Devices

dc.contributor.authorMartino, M. D. V.
dc.contributor.authorMartino, J. A.
dc.contributor.authorAgopian, P. G. D. [UNESP]
dc.contributor.authorRooyackers, R.
dc.contributor.authorSimoen, E.
dc.contributor.authorCollaert, N.
dc.contributor.authorClaeys, C.
dc.contributor.authorIEEE
dc.contributor.institutionUniversidade de São Paulo (USP)
dc.contributor.institutionUniversidade Estadual Paulista (Unesp)
dc.contributor.institutionImec
dc.contributor.institutionKatholieke Univ Leuven
dc.date.accessioned2019-10-04T19:12:24Z
dc.date.available2019-10-04T19:12:24Z
dc.date.issued2017-01-01
dc.description.abstractThe aim of this work is to study, for the first time, the behavior of differential pair circuits designed with Line TFETs and compare the suitability of this technology with alternatives such as FinFETs and Point TFETs. The first part highlights experimental characteristics of individual Line TFET transistors, which present similar transconductance and better output conductance when compared to FinFETs, while revealing better transconductance and worse output conductance in comparison to Point TFETs. Next, the experimental data for Line TFET differential pairs is presented for different bias conditions and dimensions. The last part compares the intrinsic voltage gain (A(d)), the compliance voltage and susceptibility to channel length mismatch for the 3 technologies. It is explained that Line TFET presents the highest A(d), FinFETs provides a wider operation region and Point TFETs are the least susceptible to channel length variations.en
dc.description.affiliationUniv Sao Paulo, LSI PSI USP, Sao Paulo, Brazil
dc.description.affiliationSao Paulo State Univ UNESP, Campus Sao Joao da Boa Vista, Sao Paulo, Brazil
dc.description.affiliationImec, Leuven, Belgium
dc.description.affiliationKatholieke Univ Leuven, EE Dept, Leuven, Belgium
dc.description.affiliationUnespSao Paulo State Univ UNESP, Campus Sao Joao da Boa Vista, Sao Paulo, Brazil
dc.description.sponsorshipConselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)
dc.description.sponsorshipFundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)
dc.description.sponsorshipimec's Logic Device Program
dc.format.extent3
dc.identifier.citation2017 Ieee Soi-3d-subthreshold Microelectronics Technology Unified Conference (s3s). New York: Ieee, 3 p., 2017.
dc.identifier.issn2573-5926
dc.identifier.urihttp://hdl.handle.net/11449/186355
dc.identifier.wosWOS:000463041500024
dc.language.isoeng
dc.publisherIeee
dc.relation.ispartof2017 Ieee Soi-3d-subthreshold Microelectronics Technology Unified Conference (s3s)
dc.rights.accessRightsAcesso aberto
dc.sourceWeb of Science
dc.subjectLine TFET
dc.subjectPoint TFET
dc.subjectFinFET
dc.subjectDifferential Pair
dc.subjectdifferential gain
dc.subjectdimensions mismatch
dc.titleExperimental Analysis of Differential Pairs Designed with Line Tunnel FET Devicesen
dc.typeTrabalho apresentado em evento
dcterms.licensehttp://www.ieee.org/publications_standards/publications/rights/rights_policies.html
dcterms.rightsHolderIeee

Arquivos

Coleções