Superlattices and Microstructures 100 (2016) 335e341 Contents lists available at ScienceDirect Superlattices and Microstructures journal homepage: www.elsevier .com/locate/superlat t ices Pros and cons of symmetrical dual-k spacer technology in hybrid FinFETs K.P. Pradhan a, *, M.G.C. Andrade b, P.K. Sahu a a Nano-Electronics Laboratory, Department of Electrical Engineering, National Institute of Technology, Rourkela, Odisha, 769008, India b UNESP - Univ Estadual Paulista, Group of Automation and Integrated Systems, Av. Trs de Maro, n. 511, 18087-180, Sorocaba, Brazil a r t i c l e i n f o Article history: Received 22 September 2016 Accepted 27 September 2016 Available online 29 September 2016 Keywords: Trigate FinFET Hybrid FinFET Symmetrical dual-k spacer Analog/RF Short channel effects (SCEs) * Corresponding author. E-mail addresses: k.p.pradhan@ieee.org (K.P. Pra http://dx.doi.org/10.1016/j.spmi.2016.09.043 0749-6036/© 2016 Elsevier Ltd. All rights reserved. a b s t r a c t The symmetrical dual-k spacer technology in hybrid FinFETs has been widely explored for better electrostatic control of the fin-based devices in nanoscale region. Since, high-k tangible spacer materials are broadly became a matter of study due to their better im- munity to the short channel effects (SCEs) in nano devices. However, the only cause that restricts the circuit designers from using high-k spacer is the unreasonable increasing fringing capacitances. This work quantitatively analyzed the benefits and drawbacks of considering two different dielectric spacer materials symmetrically in either sides of the channel for the hybrid device. From the demonstrated results, the inclusion of high-k spacer predicts an effective reduction in off-state leakage along with an improvement in drive current. However, these devices have paid the cost in terms of a high total gate-to- gate capacitance (Cgg) that consequently results poor cutoff frequency (fT) and delay. © 2016 Elsevier Ltd. All rights reserved. 1. Introduction The invention of 3-D FinFET technology in the semiconductor era has been considerably enabled the advancement of electronics industry and have been of immense interest for sub-20 nm applications [1,2]. The fin based devices are excellent in suppressing the short channel effects (SCEs) and have superior control over the carriers in the channel [3e7]. This improvement in technology facilitates a longer battery lifetime and energy efficient electronics in both operating regions i.e., high performance (HP) and low power (LP). According to the reported articles and International Technology Roadmap for Semiconductors (ITRS) prediction, the 3-Dimensional topology is here to expedite the profitable industries likely to 5-nm technology node [8,9]. The only modifications in lower nodes is either in physical architecture like nanowires and nano- tubes or incorporation of new materials in the channel such as Ge, GaAs, SiGe, etc. keeping the CMOS compatibility [10e12]. Today's market is more consensus about the HP consumer applications and may continue for subsequent years. The HP applications primary goal is to achieve high current drivability with higher packing density instead of bothering regarding the static leakage current [11,13]. So, to achieve the HP computing applications, a new transistor i.e., hybrid FinFET was first proposed by Zhang et al. [14]. Henceforth further modification and continuous research on hybrid devices was carried by Fahad et al. [15,9] and Pradhan et al. [11,16,17]. Hybrid FinFETs merge several technologies in a single SOI platform namely 3-D FinFET and 2-D UTB MOSFET. However, to analyze further impact of spacer technology in the hybrid FinFETs, this work in- corporates two different spacer materials symmetrically in the underlap region of either side of the channel for the hybrid dhan), gloria@sorocaba.unesp.br (M.G.C. Andrade), pksahu@nitrkl.ac.in (P.K. Sahu). mailto:k.p.pradhan@ieee.org mailto:gloria@sorocaba.unesp.br mailto:pksahu@nitrkl.ac.in http://crossmark.crossref.org/dialog/?doi=10.1016/j.spmi.2016.09.043&domain=pdf www.sciencedirect.com/science/journal/07496036 www.elsevier.com/locate/superlattices http://dx.doi.org/10.1016/j.spmi.2016.09.043 http://dx.doi.org/10.1016/j.spmi.2016.09.043 http://dx.doi.org/10.1016/j.spmi.2016.09.043 K.P. Pradhan et al. / Superlattices and Microstructures 100 (2016) 335e341336 device. Previously, the underlap FinFETs have showed immense control over SCEs [18,19]. But the major issues, which are faced by underlap FinFETs are the precise control of doping profile and an increased amount of underlap resistance. These issues arewell tackled by Refs. [18e20] with an inclusion of high-k dielectric spacers at the underlap region. Similarly, Pal et al. [21,7] have examined that superior control on the channel andmeaningful improvements are achievable in terms of Ion and Ioff by contemplating dual-k spacers over the underlap regions. The above mentioned works are carried out contemplating the high-k spacer materials in the conventional 3-D FinFET structures. In this work, we have estimated the benefits as well as drawbacks of symmetrical inclusion of dual-k spacer in either side of the channel for the hybrid devices over conventional FinFETs. The lengths of both spacers (inner high-k, Lhk, and outer low-k, Llk) are optimized for better circuit applications. The performances considered for this investigation are drive current (Ion), off state leakage current (Ioff), effective drain current (IDEFF), subthreshold slope (SS), transconductance (gm), total gate capacitance (Cgg), output conductance (gd), cutoff frequency (fT), and gain (AV). The organization of the paper is as follows: Section 2 describes the architecture of hybrid FinFETs. Section 3 presents the simulation setup that discusses the methods andmodels considered for simulating the devices. In Section 4, the investigation is done for optimizing the length of dual-k spacer and the benefits and drawbacks of the high-k spacer inclusion. Finally, the concluding observations are pointed in Section 5. 2. Hybrid FinFET architecture with symmetrical dual-k spacer technology The 3-D bird view of conventional SOI FinFET and hybrid FinFET with dual-k spacer technology architectures chosen for this work are presented in Fig. 1 (a) and (b) accordingly. Fig. 1(c) demonstrates the vertical and horizontal 2-D perspective views of both the devices. The SOI FinFET [6] offers significant control over SCEs and electrostatic parameters with a vertical thin channel and also have lesser fabrication complexity as compared to the bulk FinFET [22]. The major issues in SOI FinFET are self-heating effects because of the thick buried oxide and the cost factor. However, the self-heating effect is well-taken care by Fiegna et al. [23] and the cost factor is mitigated by the less complicated process steps. The 3-D FinFET and 2-D UTB technology are combined together to design the advanced hybrid topology. It predicts many advantages like maximum area efficiency, high packing density, and high drive current as studied in Refs. [14,9]. The key objective in this work is to establish symmetrical underlap regions at both sides of the channel towards source/drain and pattern the regions with two different dielectric spacer materials (Si3N4, k¼ 7.5 and HfO2, k¼ 22). Then the benefits and drawbacks in performances of the designed device are compared with conventional FinFET [6]. The spacer lengths of Si3N4 is termed as Llk and HfO2 as Lhk and the ratio of Llk:Lhk is varied to get an optimum ratio. The physical and electrical parameters are calibrated according to the ITRS specifications [8,6]. The SiO2 with physical thickness of 0.9 nm is considered as gate oxide. The channel is lightly doped to prevent the device from random dopant fluctuation (RDF) effect. Table 1 shows the physical dimensions for designing both the devices. Several technologies are merged in this work i.e., 3-D FinFET þ 2-D UTB þ spacer Fig. 1. (a) Typical trigate FinFET (D1) (b) Symmetrical dual-k spacer hybrid FinFET (D2, D3, D4, D5) (C) 2-D cut view of both devices. Table 1 aDevice design parameters. Parameters Nomenclature (nm) Conventional FinFET Symmetrical Dual-k hybrid FinFET WFin Fin Width 7 nm 7 nm HFin Fin Height 30 nm HFin-UTB ¼ 25 nm Lg Gate length 20 nm 20 nm UTB Ultra thin body thickness e 5 nm Llk:Lhk Length of low-k:Length of high-k 5:0 (D1) 1:4 (D2), 2:3 (D3), 3:2 (D4), 4:1 (D5) tox physical gate oxide thickness 0.9 nm 0.9 nm LT Total device length 110 nm 110 nm WT Total device width 32.2 nm 32.2 nm BOX Buried oxide thickness 40 nm 40 nm a 2013 Overall roadmap technology characteristics (ORTC) ITRS parameters for 14 nm technology node FinFET. K.P. Pradhan et al. / Superlattices and Microstructures 100 (2016) 335e341 337 engineering (two different dielectrics as inner high-k near to channel and outer low-k near to S/D in the underlap region). And a list of benefits and drawbacks for the adopted technology over conventional FinFET are systematically presented. 3. Simulation techniques Comprehensive 3-D simulations are being carried out by Sentaurus TCAD [24] to evaluate the prospective benefits and drawbacks of the hybrid device over traditional one. The numerical process and device simulations allow crucial insights on the nature of semiconductor devices that can lead to new perceptions [24]. However, the simulation needs to be properly calibrated before designing any device. Hence, the validity of the simulator has been established according to our previous work [16]. The mobility model that accounts of doping, transverse field, and velocity saturation dependency along with the drift-diffusion (DD) model are considered in the simulation. The quantum confinement effect in fin and UTB which is determined from the density gradient based quantization model is also activated in the simulation. The Lombardi high-k model is considered to dealt with the high-k related mobility degradation effects [11,12]. To avoid the poly-Si gate depletion effects, the metal gate technology is used in this work. For better comparison among the devices, the threshold voltage (Vth) is kept at an approximate value for all device cases by carefully tuning the gate metal work function. 4. Performance evaluation Fig. 2(a) shows the variation of electrostatic potential in the spacer and channel region (on state, VDS ¼ 0.7 V) for the conventional and the proposed hybrid FinFETs with increasing high-k spacer length (Lhk). It is noticed that the potential lines diverge from their path and give extra peaks at the two spacer interface near the drain side in case of hybrid FinFET. As the inner high-k spacer length increases, the potential lines are well confined with an increase amount in the channel region and interface of the two spacers, which conclusively enhances the on-current (Ion) of the device. Similarly from Fig. 2(b), a significant improvement in SS (roughly 3.14%) can be observed in case of hybrid FinFET. D2 device gives the optimum SS value i.e., 63.52 mV/decade, which is nearer to the ideal value (60 mV/decade) and the degradation occurs with decrease in Lhk. Fig. 2. Variation of electrostatic potential inside the channel and interface of the two spacers for conventional and hybrid FinFET for different Llk:Lhk ratios at VDS ¼ 0.7 V. Fig. 3. Comparison among various architectures (a) Ion (b) Ioff. Fig. 4. Non-normalized ID�VGS performance analysis between conventional SOI FinFET and hybrid FinFETs at different Llk:Lhk ratios for (a) VDS ¼ 50 mV (b) VDS ¼ 0.7 V. K.P. Pradhan et al. / Superlattices and Microstructures 100 (2016) 335e341338 An identical analogy can be made for Ion and Ioff of our proposed device, which are presented in Fig. 3(a) and (b). The non- normalized on-current is compared between conventional FinFET and different topologies of hybrid channel FinFET in Fig. 3(a). The drive current of any device plays an important role in HP consumer applications. Hence, it is crucial to perceive the response of inner high-k spacer length (Lhk) on Ioff and Ion. A sharp increase in Ion is identified with increase in Lhk up to an optimum value of 4 nm. The D2 (Llk:Lhk ¼ 1:4) architecture exhibits highest enhancement in Ion (around 1.23x) from the conventional one i.e., D1. This increase in Ion is partially because of the UTB (hybrid channel) and due to the inclusion of larger Lhk, which further modulates the carrier concentration in underlap region. Comparative analysis of Ioff for different archi- tectures is given in Fig. 3(b). The hybrid FinFETs with Llk:Lhk ¼ 1:4 shows an almost 60% of reduction in off-state leakage current as compared to conventional one. Fig. 4(a) and (b) compare the transfer characteristic among conventional and hybrid FinFETs at different Llk:Lhk ratios for both low and high VDS. It can be observed that the inclusion of dual-k spacer over the underlap regions of the proposed hybrid FinFETs can able to deliver 66.66% higher non-normalized drive current with the same chip area as compared to conventional FinFET. Each nanometer increase in Lhk spacer of the hybrid FinFET leads to a increase in Ion. This enhancement in Ionwith Lhk is because of the gate fringe induced barrier lowering (GFIBL) in the underlap region [18]. Fig. 5. Non-normalized ID � VDS performance comparison among conventional SOI FinFET and hybrid FinFETs at different Llk:Lhk ratios for (a) VGS ¼ VDD/2 (b) VDS ¼ VDD. Fig. 6. gm�ID performance analysis between conventional SOI FinFET and hybrid FinFETs at different Llk:Lhk ratios for (a) VDS ¼ 50 mV (b) VDS ¼ 0.7 V. K.P. Pradhan et al. / Superlattices and Microstructures 100 (2016) 335e341 339 The ID�VDS of the hybrid FinFETs with spacer technology are compared to the conventional FinFET at VGS ¼ VDD=2 and VGS¼VDD as shown in Fig. 5(a) and (b) respectively. IDLOW (VGS ¼ VDD=2;VDS ¼ VDD) and IDHIGH (VGS ¼ VDD;VDS ¼ VDD=2) are calculated to evaluate the effective drain current (IDEFF ¼ ðIDLOW þ IDHIGHÞ=2), which estimates the effective drain current drawn during switching. It is more realistic and way less optimistic than IDSat assessment. By observing the inset values of IDLOW and IDHIGH from Fig. 5, it is clear that the device having high Lhk provide more IDEFF. The D2 device (Llk:Lhk ¼ 1:4) delivers IDEFF ¼ (20.29 þ 79.05)/2 mA ¼ 49.67 mA, which is optimum from any other cases and is nearly 7.6% higher than the con- ventional FinFET (D1). Fig. 6(a) and (b) show the plot of gm for a conventional FinFETand different topologies of hybrid FinFETswith varying Llk:Lhk ratio at high (VDS ¼ 0.7 V) and low (VDS ¼ 50 mV). To analyze the immense improvement in gm (vID/vVGS) with an increase in Llk:Lhk spacer ratio, we have evaluated and studied the ID � gm curve. According to the literature, access resistance problem is more serious in conventional trigate FinFETs. However, some solutions are available like increasing the HFin out of the gate region [25]. The parasitic resistance problem can be avoided by using a UTB in FinFET technology, i.e., hybrid FinFETs with higher Lhk spacer length, which further increases the drain current. This is also validated from Figs. 4e6, both the parameters i.e., on-current, IDEFF, and gm are increasing with the increase in Lhk in hybrid FinFETs. This is primarily due to the fringing field induced inversion charge modulation inside the underlap region. The charge-based model of gm for undoped multigate MOSFETs are represented as [26]: gm ¼ vID=vVGS ¼ � mW . Leff � ðQS � QDÞ (1) where QD and QS represent the gate-to-drain and gate-to-source charges, m is the electron mobility, W, and Leff are the width and effective channel length of the device. From Eq. (1), the gm is directly related to the source/drain charge difference (QS � QD) and m. In subthreshold region (low VDS and VGS), the QS of the hybrid FinFETs increases moderately because of the immense gate control and in themean time QD remains almost constant as the gate induced fringing field is negligible. Hence, QS�QD increases rapidly resulting a high subthreshold gm (Fig. 6(a)). Similarly, with an increase in Lhk, the reverse gate-to- drain field plays a significant role, which further reduces the QD. As a result, gm increases with increase in Lhk in sub- threshold region and showsmaximum for D2 device case (Llk:Lhk¼1:4). But, in superthreshold region (high VDS), the m term is very high and dominates gm. Again, increasing Lhk in superthreshold region, theQD escalateswith a unchangedQS that reduces QS�QD term of Eq. (1). However, due to the improved mobility for high Lhk devices, there is a minor increment in gm can be noticed at superthreshold region (Fig. 6(b)). Fig. 7 (a) illustrates the output conductance (gd) for conventional and hybrid FinFETs at VGS¼ 0.7 V. The gd can be expressed as [26]. Fig. 7. Analog parameters analyzed among hybrid FinFETs with different Llk:Lhk ratios and conventional FinFET (a) Output conductance (gd) at VGS ¼ 0.7 V (b) gain (gm=gd). Fig. 8. Comparison of (a) Cgg � ID (b) fT � ID, among hybrid FinFETs with different Llk:Lhk ratios and conventional FinFET at VDS ¼ 0.7 V. K.P. Pradhan et al. / Superlattices and Microstructures 100 (2016) 335e341340 gd ¼ vID=vVDS ¼ � mW . Leff � QD (2) The interpretation of above variables are well explained under Eq. (1). From Eq. (2), gd increases proportionately with QD. In earlier analogy under Fig. 6(b), we have perceived that QD plays a significant role in superthreshold region (high VDS) and become the dominating factor for high Lhk devices. So, it is observed from Fig. 7(a) that with increase in Lhk, the gate induced fringing field increases, which further enhances the QD and increases the gd in superthreshold region. However, there is a reverse effect in subthreshold region i.e., gd decreases with increase in Lhk as QD remains constant at subthreshold region. For analog performances, the gain (AV ¼ gm=gd) of the device is an important figure of merits (FOMs) that is analyzed in Fig. 7(b). From Fig. 7(b), in subthreshold region, AV is dominated by gm as a result, AV increases with increase in Lhk that is due to higher gm as discussed in Fig. 6. And just a reverse phenomena is noticed in the superthreshold region. This is because of the gd factor as argued in Fig. 7(a). The variation of total gate capacitance (Cgg), and cutoff frequency ðfT ¼ gm=ð2pCggÞÞ with respect to ID for conventional FinFET and different architectures of hybrid FinFETs are shown in Fig. 8(a) and (b) respectively. It is seen that Cgg increases with the increase in ID, and the increment is higher for larger Lhk hybrid FinFETs because of the advancement in the gate side wall developed fringing field lines. So, Cgg increases whereas gm is almost constant for hybrid devices in the superthreshold region as shown in Fig. 6(b). Hence, the increase in Cgg dominates the fT for the proposed devices consequently a decline in fT is observed in case of hybrid devices as demonstrated in Fig. 8(b). 5. Conclusion This paper illustrates the benefits and drawbacks of hybrid FinFETs (UTB þ FinFET þ Spacer engineering) with compare to conventional FinFETs for subsequent technology nodes. The impact of dual-k spacers (inner high-k (HfO2) and outer low-k (Si3N4)) in improving the performances of the hybrid devices have been analyzed. The proposed device with an optimal high- k spacer length (Lhk) can be efficiently reduce the SS and Ioff with an improved Ion. The D2 topology i.e., hybrid FinFET with Llk:Lhk ¼ 1:4 exhibits superior electrostatic integrity in both Ion and Ioff, which in turn enhance the overall device performance. Nonetheless, D2 architecture shows a 1.23x improvement in Ion, and around 60% reduction in Ioff as compared to SOI FinFET that is required for high speed, and low power consumption applications. We have also demonstrated the influence of Llk:Lhk ratios on various analog/RF FOMs like gm, AV, and fT in both subthreshold and superthreshold region of operations. From the presented outcomes, it is concluded that the hybrid FinFETs with higher Llk:Lhk ratios are outperformed as compared to conventional FinFET with regard to Ioff, Ion and gm. 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Introduction 2. Hybrid FinFET architecture with symmetrical dual-k spacer technology 3. Simulation techniques 4. Performance evaluation 5. Conclusion References