Semiconductor Science and Technology PAPER Analysis of proton irradiated n- and p-type strained FinFETs at low temperatures down to 100 K To cite this article: Luis Felipe Vicentis Caparroz et al 2018 Semicond. Sci. Technol. 33 065003   View the article online for updates and enhancements. Related content Analog performance of standard and uniaxial strained triple-gate SOI FinFETs under x-ray radiation C C M Bordallo, F F Teixeira, M A G Silveira et al. - Assessment of DC and low frequency noise performances of triple-gate FinFETs at cryogenic temperatures B Cretu, D Boudier, E Simoen et al. - Effect of the back bias on the analog performance of standard FD and UTBB transistors-based self-cascode structures Rodrigo T Doria, Denis Flandre, Renan Trevisoli et al. - This content was downloaded from IP address 186.217.236.60 on 05/06/2019 at 20:40 https://doi.org/10.1088/1361-6641/aabab3 http://iopscience.iop.org/article/10.1088/0268-1242/29/12/125015 http://iopscience.iop.org/article/10.1088/0268-1242/29/12/125015 http://iopscience.iop.org/article/10.1088/0268-1242/29/12/125015 http://iopscience.iop.org/article/10.1088/0268-1242/31/12/124006 http://iopscience.iop.org/article/10.1088/0268-1242/31/12/124006 http://iopscience.iop.org/article/10.1088/0268-1242/31/12/124006 http://iopscience.iop.org/article/10.1088/1361-6641/aa7659 http://iopscience.iop.org/article/10.1088/1361-6641/aa7659 http://iopscience.iop.org/article/10.1088/1361-6641/aa7659 https://oasc-eu1.247realmedia.com/5c/iopscience.iop.org/298984340/Middle/IOPP/IOPs-Mid-SST-pdf/IOPs-Mid-SST-pdf.jpg/1? Analysis of proton irradiated n- and p-type strained FinFETs at low temperatures down to 100K Luis Felipe Vicentis Caparroz1, Caio Cesar Mendes Bordallo1, Joao Antonio Martino1, Eddy Simoen2, Cor Claeys3 and Paula Ghedini Der Agopian1,4 1 LSI/PSI/USP—University of Sao Paulo, Sao Paulo, Brazil 2 imec, Leuven, Belgium 3E.E. Dept, KU Leuven, Leuven, Belgium 4UNESP—Universidade Estadual Paulista, São João da Boa Vista, Brazil E-mail: agopian@lsi.usp.br Received 15 February 2018, revised 26 March 2018 Accepted for publication 29 March 2018 Published 25 April 2018 Abstract This paper studies the main low temperature electrical parameters of SOI n- and p-type FinFETs, standard and strained devices, submitted to proton irradiation. The study covers the range from room temperature down to 100 K, focusing on the threshold voltage (VTH), subthreshold swing (SS), the Early voltage VEA, transistor efficiency and the intrinsic gain voltage (AV) for 3 different channel widths. The p-channel devices showed a greater immunity to radiation than the n-channel ones, when considering the basic parameters thanks to the back conduction turn-off tendency, while from the analog parameters point of view, both transistor types presented a similar response to proton radiation at strong inversion. Keywords: strained devices, proton radiation, low temperature, FinFETs (Some figures may appear in colour only in the online journal) 1. Introduction Silicon-on-insulator (SOI) technology has shown an improved performance in special applications that may involve harsh environments such as radiation and high temperatures. The presence of a buried oxide beneath the thin silicon active region allows for a higher tolerance to transient radiation effects, mainly for fully depleted SOI devices, which have better electrostatic coupling than bulk devices [1]. However, the buried oxide is usually thick and makes the device more susceptible to total ionization dose (TID) effects, mainly due to positive charge buildup [2]. The radiation effects in MOS oxides was extensively studied and it is reported in [3]. In the challenge of device downscaling, SOI is also a pro- minent technology. To overcome short-channel effects and other parasitics that may arise from reducing the physical size, the semiconductor industry has developed new techniques, i.e., strain engineering, high-κ dielectrics and novel architectures, such as non-planar (three-dimensional -3D) and multiple gate structures. A vertical triple gate transistor (FinFET) is one of the candidates for commercial and special applications where fitting these scaling requirements are necessary. Its structure aims for the improvement of electrostatic coupling and better control of short-channel effects (SCE) than traditional planar devices. By using narrow-fin devices a high radiation toler- ance can be achieved [4]. Considering that the effects of low temperature on strained FinFET devices are not fully explored yet, and also that there are some applications where transistors are submitted to radiation, such as for aerospace and medical equipment, this work aims to evaluate the low temperature impact on the main electrical parameters of strained FinFETs submitted to proton radiation. 2. Device characteristics The triple gate SOI FinFETs analyzed in this work were fabricated at imec, Belgium, on SOI substrates with a 150 nm Semiconductor Science and Technology Semicond. Sci. Technol. 33 (2018) 065003 (10pp) https://doi.org/10.1088/1361-6641/aabab3 0268-1242/18/065003+10$33.00 © 2018 IOP Publishing Ltd Printed in the UK1 https://orcid.org/0000-0002-0886-7798 https://orcid.org/0000-0002-0886-7798 mailto:agopian@lsi.usp.br https://doi.org/10.1088/1361-6641/aabab3 http://crossmark.crossref.org/dialog/?doi=10.1088/1361-6641/aabab3&domain=pdf&date_stamp=2018-04-25 http://crossmark.crossref.org/dialog/?doi=10.1088/1361-6641/aabab3&domain=pdf&date_stamp=2018-04-25 thick SiO2 layer (BOX). The gate dielectric is composed by a 2 nm HfSiON layer over a 1 nm SiO2 interfacial layer, resulting in a 1.5 nm equivalent oxide thickness (EOT). The midgap gate is composed of 10 nm of TiN capped by 100 nm of poly-silicon. All devices have a fin height of 65 nm and the source and drain series resistance were reduced by selective epitaxial regrowth. A schematic lay-out of the studied Fin- FETs is shown in figure 1. In this work, two different channel lengths (LG), 150 nm and 900 nm have been considered and three different fin widths (WFin), 20 nm, 120 nm and 370 nm. More process details can be found in [5]. Additionally two different splits were analyzed: an unstrained split that was taken as a reference and a strained one. In the last case, the strained split combines biaxial (sSOI substrates) and uniaxial stress (dual contact etch stop layer— dCESL). The dCESL technique consists of a deposition of an SiNx cap over the gate stack, which can result in a com- pressive or tensile strain in the channel, depending on the amount of hydrogen and some processing parameters [6]. Since both p and n-type devices are evaluated, the dCESL is appropriate because while compressive strain enhances the hole mobility, tensile strain benefits the electron mobility. The devices were irradiated at the Cyclone facility in Louvain-la-Neuve (Belgium), using 60MeV beam energy, with a fluence of 1012 p/cm2 at room temperature. No bias was applied during irradiation and the contacts were kept floating. 3. Analysis and discussion 3.1. Basic parameters Figure 2 shows the experimental threshold voltage (VTH) for a temperature range from room temperature down to 100 K, for both n-type (figure A) and p-type transistors (figure B), before and after proton radiation and for 3 different channel widths (WFin). Considering that for 3D devices, not only the channel length but the W/L ratio is important when the SCE are taken into account, for the widest studied transistor (WFin=370 nm) a long channel device was also evaluated, aiming to minimize the SCE and to better understand the proton irradiation influ- ence on the FinFET behavior. Both types of transistors (nMOS and pMOS) presented a VTH absolute value increase as the temperature decreases. One can notice that this VTH increase is almost linear with the temperature reduction and can be explained by the Fermi level potential shift towards the majority carrier band edge upon cooling. Another general evaluation is the comparison between strained and unstrained devices. Strained devices present smaller VTH values compared with their counterparts, since the mechanical stress causes a valence and conduction band offset, resulting in a bandgap narrowing and, conse- quently, a VTH reduction. However, when the focus is on the proton radiation effects, it is possible to observe that it affects the n-type and p-type transistors in a different way. When nFinFETs were irradiated, positive charges build up in the oxides. Con- sidering the thickness of the buried oxide, it causes a negative VTH shift at the back interface resulting in a parasitic back conduction. It is equivalent to the application of a positive back-gate bias, inverting the back interface. On the other hand, for the pFinFETs, the effect of the radiation induced positive charges in the buried oxide on VTH (negative shift) which turns off the back interface parasitic current, thus improving the device character- istic [7]. When the results were evaluated for low temperatures, the effectiveness of stress should be taken into account, because while for MOSFET technology the modulus of VTH increases at low temperatures, the strain effectiveness also increases reducing the VTH value. In addition, the higher the strain effectiveness, the higher the interface charges even before radiation. As a result, it is possible to observe that for strained devices the VTH is slightly less affected by radiation as the temperature goes down. The same VTH trend was obtained for both channel lengths (150 nm and 900 nm) after radiation. The same analysis was performed for the subthreshold swing (SS) as a function of temperature (figure 3). For both types of transistors (n and p) the devices with a narrow fin (WFin=20 nm) showed to be tolerant to radiation, pre- senting almost no variation independent of the mechanical stress and temperature. Wider FinFETs however, are more affected by radiation since there is a lower electrostatic coupling between the sidewall gates and the back channel. As explained before, these buried charges created by the radiation cause a back conduction for n-channel devices and turns off this parasitic current for p-channel ones. This opposite behavior of the back conduction results in an Figure 1. FinFET structure. 2 Semicond. Sci. Technol. 33 (2018) 065003 L F V Caparroz et al opposite trend of SS comparing p and n transistors. While the radiation degrades the SS behavior for nFinFETs, it reduces the p-type transistor off current [7, 8]. Analyzing the temperature influence on SS for unstrained devices, the reduction of SS with temperature is almost linear as expected [9], but it is non-linear for both types of strained FinFETs. This is explained as follows: although the mechanical stress improves the ON current, it results in a high interface trap density (Nit) [10] that tends to degrade the SS values. Then, for strained devices both effects (Nit and VTH variation) should be taken into account. Considering that at low temperatures the VTH is less affected by irradiation and Nit has a higher impact on SS, a non-linear SS reduction with temperature was obtained for strained transistors. For p-type devices, when the temperature goes down, the increase of VTH results in a suppression of the back parasitic conduction. Since the radiation effects on VTH follow the same trend, it is possible to conclude that the best behavior of Figure 2. Experimental threshold voltage as a function of temperature for strained and unstrained devices, before and after radiation for nFinFETs (A) and pFinFETs (B). In case of nFinFET with WFin=370 nm, two LG values are analyzed. 3 Semicond. Sci. Technol. 33 (2018) 065003 L F V Caparroz et al the back interface (in the studied temperature range) occurs at 100 K. Both effects contribute to the SS improvement, which remains near the theoretical value at 100 K (20 mV/dec) independent of WFin. Analyzing the transconductance (gm), figure 4 presents the normalized transconductance (gm/Weff) as a function of front gate voltage VGS at room temperature, comparing both splits, before and after proton irradiation. Considering only the tensile stress effectiveness, it can be noticed that for strained devices a higher transconductance is obtained due to the enhancement of the electron mobility. Adding the radiation effects to this analysis, a gm degradation was observed for irradiated devices, as expected. Figure 3. Experimental subthreshold swing as a function of temperature for strained and unstrained devices, before and after radiation for nFinFETs (A) and pFinFETs (B). In case of nFinFET with WFin=370 nm, two LG values are analyzed. Figure 4. Normalized transconductance as a function of front gate voltage at room temperature; for strained and unstrained devices, before and after radiation for LG=150 nm. 4 Semicond. Sci. Technol. 33 (2018) 065003 L F V Caparroz et al However, strained transistors, present a higher gm degradation because tensile strain introduces more interface traps, which reduces the electron mobility by Coulomb scat- tering [11] and the proton irradiation may increase that. In addition, strained narrow-fin devices are more affected by radiation, because their small geometry results in a small effect of biaxial strain and the lattice defects and traps may be more significant. Another observation is that wider fin devices present higher gm due to the different electron mobility at each interface caused by a different crystallographic orientation. The top interface is (100) and in this plane electrons have higher mobility than in the side interfaces, which are (110) [12]. Since the carrier mobility changes with crystallographic orientation, the fin geometry plays an important role in the effective mobility. Thus, for wide FinFETs, the top mobility (μtop) is more important, while for narrow-fin devices, the sidewall mobility (μside) has a higher influence on μeff. Another important consideration is that in the (100) plane the Figure 5. Effective mobility as a function of temperature for different fin widths, for strained and unstrained devices, before and after radiation for nFinFETs (A) and pFinFETs (B). 5 Semicond. Sci. Technol. 33 (2018) 065003 L F V Caparroz et al electron mobility is higher, while it is better in the (110) sidewalls for the hole mobility. Putting all these elements together, one can understand why for n-type transistors a higher effective mobility is obtained for wide FinFETs and for p-type devices the better results were obtained for narrow devices (figure 5). The transconductance analyses also pointed out the radiation and low temperature effects on the effective mobi- lity (μeff), a parameter extracted by the Y-function method [13], for all measured devices, and presented in figure 5. Focusing on the temperature influence on mobility, an improvement of the mobility when the temperature decreases for both types of transistors is observed, as expected [14]. However, the radiation effect degrades this parameter due to the increase of the lattice defects, it is possible to observe a smaller mobility increase as temperature goes down, showing a higher radiation influence on μ0, eff at 100 K. Only for wider and strained n-type FinFETs at 100 K the obtained mobility after radiation seems to be higher than before. This unexpected result can be explained by the back conduction that is high enough to cause a gm ramp (figure 6) due to a different mobility of the front and back interfaces [15] and when it occurs the Y function method is no longer valid. 3.2. Analog parameters The analog analysis is based on the intrinsic voltage gain (AV), the transistor efficiency (gm/IDS), the early voltage (VEA) and the output conductance (gD). The intrinsic voltage gain is calculated by equation (1). = * =∣ ∣ ( )A gm I V gm g 1V DS EA D Figure 7 presents the temperature and proton radiation influence on the narrow and strained nFinFET efficiency as a function of the inversion coefficient [16]. The narrow and strained device was chosen due to its better basic performance parameters (high mobility and better gate coupling). Focusing on the low temperature influence on gm/IDS, it is possible to observe an improvement of this parameter at 100 K reaching about 90 V A−2 at weak inversion. This is due to the temperature impact on the SS behavior that results in a lower SS value. At strong inversion the same trend was obtained due to the electron mobility enhancement. However, the proton radiation acts in the opposite direction to the temperature. The radiation tends to degrade the gm/IDS in all inversion regimes. At weak inversion the degradation is caused by the interface states that increase the SS value and consequently the transistor efficiency and at strong inversion the main radiation effect is the mobility degradation. The effect of the proton radiation is more significant at weak inversion than at strong one. The same gm/IDS trend was obtained for pFinFETs. Figure 8 presents the output conductance (gD) behavior as a function of temperature for both (p and n) transistors for |VDS|=1 V and |VGT|=0.2 V. Evaluating all fin widths, a gD increase was obtained reducing the temperature, due to two different mechanisms at low temperatures: the impact ionization rate increase and the higher carrier mobility. However, for devices with a strong coupling between gates (narrow devices) the gD degradation at low temperatures is smaller, so that the impact ionization rate could be the predominant effect on the gD behavior. Similar for lowering of the temperature, the use of strain increases gD due to the enhancement of the electron mobility. It can be noticed that the temperature impact on gD is pre- dominant compared with radiation and mechanical stress effects. Figure 6. Experimental drain current and transconductance as a function of gate bias for strained nFinFET. Figure 7. gm/IDS ratio as a function of inversion coefficient for strained nFinFETs, at different temperatures. 6 Semicond. Sci. Technol. 33 (2018) 065003 L F V Caparroz et al Although the VEA behavior usually follows the same trend of gD, analyzing figure 9, one can conclude that the VEA is independent of temperature. Similar to the output conduc- tion, VEA also depends on both mechanisms discussed earlier. However, thinking about the VEA behavior, there is compe- tition between these effects. While the impact ionization rate increase tends to degrade the VEA, the higher carrier mobility results in a higher drain current level, which tends to improve the VEA value. Based on this competition, and on the almost flat VEA behavior, it is possible to conclude that in the studied temperature range both effects have almost the same impact on VEA and cancel each other out. The same behavior was obtained for both types of transistors. One way of putting together the radiation and temper- ature effects on the investigated analog parameters is to evaluate the intrinsic voltage gain (AV) that is presented for Figure 8. Output characteristic as a function of temperature for different fin widths, for strained and unstrained devices, before and after radiation for nFinFETs (A) and pFinFETs (B). 7 Semicond. Sci. Technol. 33 (2018) 065003 L F V Caparroz et al Figure 9. Early voltage behavior at low temperatures for different fin widths, for strained and unstrained devices, before and after radiation for nFinFETs (A) and pFinFETs (B). 8 Semicond. Sci. Technol. 33 (2018) 065003 L F V Caparroz et al |VDS|=1 V and |VGT|=0.2 V in figure 10. From this figure it is possible to see that AV at strong inversion is slightly affected by temperature even for irradiated devices. It can be explained by the fact that at low temperatures, in the strong inversion regime, both the drain current (IDS) and gm increase due to the carrier mobility, results in only a small gm/IDS rate variation. Since the intrinsic gain voltage depends on this ratio and the VEA values, the AV keeps the same VEA tendency. The same explanation can be used for both nFinFETs and pFinFETs. In summary, the pFinFETs have a better performance when looking at digital parameters like SS after irradiation, mainly due to the negative shift of VTH caused by the charge buildup in the BOX. However, nFinFETs and pFinFETs Figure 10. Intrinsic Voltage Gain (AV) at low temperatures for different fin widths, for strained and unstrained devices, before and after radiation for nFinFETs (A) and pFinFETs (B). 9 Semicond. Sci. Technol. 33 (2018) 065003 L F V Caparroz et al present similar behavior in terms of the analyzed analog parameters at strong inversion. 4. Conclusion The proton irradiation effects of SOI FinFETs were evaluated from room temperature down to 100 K. Both n-channel and p-channel devices have been studied, with and without channel strain. Narrow fin devices (20 nm) are practically radiation insensitive in all cases. The influence of both temperature and radiation is more noticeable on wider devi- ces, mainly on the strained ones, where the effects of oxide and interface traps turned out to be more significant. The pFinFET presented an improvement with radiation concerning some basic parameters due to the turn-off of the parasitic back current. On the other hand the nFinFETs degrade due to the presence of the parasitic back current which increases in these transistors. For the analog parameters studied in this paper, both FinFET types present similar results at strong inversion. Acknowledgments The authors would like to thank CNPq and FAPESP for the financial support during the execution of this work. Part of the work has been performed within the frame of imec’s Core Partner program on Logic Devices. ORCID iDs Paula Ghedini Der Agopian https://orcid.org/0000-0002- 0886-7798 References [1] Colinge J P 2008 FinFETs and Other Multi-Gate Transistors 1st edn (New York: Springer) p 1–48 [2] Schwank J R, Ferlet-Cavrois V, Shaneyfelt M R, Paillet P and Dodd P E 2003 Radiation effects in SOI technologies IEEE Trans. Nucl. Sci. 50 522–38 [3] Schwank J R, Shaneyfelt M R, Fleetwood D M, Felix J A, Dodd P E, Paillet P and Ferlet-Cavrois V 2008 Radiation effects in MOS oxides IEEE Trans. Nucl. Sci. 55 1833–53 [4] Colinge J P 2008 FinFETs and Other Multi-Gate Transistors 1st edn (New York: Springer) p 257–91 [5] Collaert N, Rooyackers R, Clemente F, PZimmerman P, ICayrefoureq I, Ghyselen B, San K T, Eyckens B, Jurczak M and Biesemans S 2006 Performance enhancement of MUGFET devices using super critical strained-SOI (SC- SSOI) and CESL Proc. Symp. VLSI Technology pp 52–3 Digest of Technical Papers [6] Sleeckx E, Schaekers M, Shi X, Kunnen E, Degroote B, Jurczak M and de Potter de ten Broeck M A E 2005 Optimization of low temperature silicon nitride processes for improvement of device performance Microelectron. Rel. 45 865–8 [7] Agopian P G D, Martino J A, Kobayashi D, Simoen E and Claeys C 2012 Influence of 60 MeV proton-irradiation on standard and strained n- and p-channel MuGFETs IEEE Trans. Nucl. Sci. 59 707–13 [8] Mamouni F E, Zhang E X, Schrimpf R D, Fleetwood D M, Reed R A, Cristoloveanu S and Xiong W 2009 Fin-width dependence of ionizing radiation-induced subthreshold- swing degradation in 100 nm-gate-length FinFETs IEEE Trans. Nucl. Sci. 56 3250–5 [9] Colinge J P et al 2006 Temperature effects on trigate SOI MOSFETs IEEE Electron Device Lett. 27 172–4 [10] Kobayashi D, Simoen E, Put S, Griffoni A, Poizat M, Hirose K and Claeys C 2011 Proton-induced mobility degradation in finfets with stressor layers and strained SOI substrates IEEE Trans. Nucl. Sci. 58 800–7 [11] Put S, Simoen E, Collaert N, Claeys C, Van Uffelen M and Leroux P 2007 Geometry and strain dependence of the proton radiation behavior of MuGFET devices IEEE Trans. Nucl. Sci. 54 2227–32 [12] Rudenko T, Kilchytska V, Collaert N, Jurczak M, Nazarov A and Flandre D 2008 Carrier mobility in undoped triple-gate FinFET structures and limitations of its description in terms of top and sidewall channel mobilities IEEE Trans. Electron Devices 55 3532–41 [13] Subramanian N, Ghibaudo G and Mouis M 2010 Parameter extraction of nano-scale MOSFETs using modified Y function method European Solid State Device Research Conf. (ESSDERC) pp 309–12 [14] Wolpert D and Ampadu P 2008 Managing Temperature Effects in Nanoscale Adaptative Systems (Berlin: Springer) p 15–33 [15] Martino J A, Agopian P G D, Collaert N, Simoen E and Claeys C 2009 Transconductance ramp effect in high-k triple gate sSOI nFinFETs IEEE Int. SOI Conf. [16] Willy M C S 2006 Analog Design Essentials 1st edn (Netherlands: Springer) p 23–36 10 Semicond. Sci. Technol. 33 (2018) 065003 L F V Caparroz et al https://orcid.org/0000-0002-0886-7798 https://orcid.org/0000-0002-0886-7798 https://orcid.org/0000-0002-0886-7798 https://orcid.org/0000-0002-0886-7798 https://orcid.org/0000-0002-0886-7798 https://doi.org/10.1109/TNS.2003.812930 https://doi.org/10.1109/TNS.2003.812930 https://doi.org/10.1109/TNS.2003.812930 https://doi.org/10.1109/TNS.2008.2001040 https://doi.org/10.1109/TNS.2008.2001040 https://doi.org/10.1109/TNS.2008.2001040 https://doi.org/10.1016/j.microrel.2004.10.028 https://doi.org/10.1016/j.microrel.2004.10.028 https://doi.org/10.1016/j.microrel.2004.10.028 https://doi.org/10.1016/j.microrel.2004.10.028 https://doi.org/10.1109/TNS.2012.2187070 https://doi.org/10.1109/TNS.2012.2187070 https://doi.org/10.1109/TNS.2012.2187070 https://doi.org/10.1109/TNS.2009.2034155 https://doi.org/10.1109/TNS.2009.2034155 https://doi.org/10.1109/TNS.2009.2034155 https://doi.org/10.1109/LED.2006.869941 https://doi.org/10.1109/LED.2006.869941 https://doi.org/10.1109/LED.2006.869941 https://doi.org/10.1109/TNS.2011.2109967 https://doi.org/10.1109/TNS.2011.2109967 https://doi.org/10.1109/TNS.2011.2109967 https://doi.org/10.1109/TNS.2007.911420 https://doi.org/10.1109/TNS.2007.911420 https://doi.org/10.1109/TNS.2007.911420 https://doi.org/10.1109/TED.2008.2006776 https://doi.org/10.1109/TED.2008.2006776 https://doi.org/10.1109/TED.2008.2006776 1. Introduction 2. Device characteristics 3. Analysis and discussion 3.1. Basic parameters 3.2. Analog parameters 4. Conclusion Acknowledgments References