Martino, LoaoMesquita, ViniciusMacambira, ChristianItocazu, VitorAlmeida, LucianoAgopian, Paula [UNESP]Simoen, EddyClaeys, CorJiang, Y. L.Tang, T. A.Huang, R.2019-10-042019-10-042016-01-012016 13th Ieee International Conference On Solid-state And Integrated Circuit Technology (icsict). New York: Ieee, p. 785-788, 2016.http://hdl.handle.net/11449/184617In this work the Zero Temperature Coefficient (ZTC) is investigated experimentally using state-of-the-art industrial technologies like Ultra-Thin Body and Buried Oxide (UTBB) and triple-gate FinFETs (irradiated and/or strained devices), both fabricated on Silicon On lnsulator (SOI) wafers. A simple analytical model to analyze the behavior of the gate-source voltage at the Zero Temperature Coefficient point (V-ZTC) is validated for these advanced devices. Although simple, the model predictions have shown good agreement with the experimental results and can be useful for low-power low-voltage analog circuit designers, where biasing at/near the ZTC point should result in low thermal drift of the circuit operation.785-788engTrabalho apresentado em eventoWOS:000478951000217Acesso aberto04969095954656960000-0002-0886-7798