Elaraby, NahlaFrismuth, DavidFilho, Nilson Neves [UNESP]Jantsch, Axel2023-07-292023-07-292022-01-01IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, v. 2022-October.2324-84402324-8432http://hdl.handle.net/11449/246361The ever-expanding need for low-power devices can be approached by implementing approximate computing methods. A restrictive energy budget is met by dropping the concept of fully exact or entirely deterministic computations. We propose a methodology to trade off accuracy with run-time power consumption through Dynamic Partial Reconfiguration (DPR) of Field Programmable Gate Arrays (FPGAs). Optimization is done by switching between predefined design configurations and combining exact and approximate versions of the most power-consuming circuit blocks. We designed a dynamic reconfiguration manager to select and configure the FPGA with the appropriate partial bitstream. The reconfiguration is executed automatically at run time according to the system power state and the accuracy requirement of the running application. The experimental results show that the proposed mechanism can achieve between 10% and 58% power reduction with a maximum error of 0.35 and an average error range of 0.1 beside negligible reconfiguration energy cost.engApproximate ComputingFPGARun time PowerTrabalho apresentado em evento10.1109/VLSI-SoC54400.2022.99396392-s2.0-85142459949