de Oliveira, TiagoMarranghello, Norian [UNESP]2014-05-202014-05-202011-05-01Neurocomputing. Amsterdam: Elsevier B.V., v. 74, n. 10, p. 1510-1519, 2011.0925-2312http://hdl.handle.net/11449/21777This paper deals with the design of a network-on-chip reconfigurable pseudorandom number generation unit that can map and execute meta-heuristic algorithms in hardware. The unit can be configured to implement one of the following five linear generator algorithms: a multiplicative congruential, a mixed congruential, a standard multiple recursive, a mixed multiple recursive, and a multiply-with-carry. The generation unit can be used both as a pseudorandom and a message passing-based server, which is able to produce pseudorandom numbers on demand, sending them to the network-on-chip blocks that originate the service request. The generator architecture has been mapped to a field programmable gate array, and showed that millions of numbers in 32-, 64-, 96-, or 128-bit formats can be produced in tens of milliseconds. (C) 2011 Elsevier B.V. All rights reserved.1510-1519engPseudorandom number generationIntelligent systemsReconfigurable architecturesNetwork-on-chipArtigo10.1016/j.neucom.2010.12.021WOS:000290838600002Acesso restrito20986232628927190000-0003-1086-3312