Itocazu, Vitor T.Almeida, Luciano M.Sonnenberg, VictorAgopian, Paula G. D. [UNESP]Barraud, SylvainVinet, MaudFaynot, OlivierMartino, Joao A.2018-12-112018-12-112017-11-15SBMicro 2017 - 32nd Symposium on Microelectronics Technology and Devices: Chip on the Sands, co-located Symposia: 30th SBCCI - Circuits and Systems Design, 2nd INSCIT - Electronic Instrumentation, 7th WCAS - IC Design Cases and 17th SForum - Undergraduate-Student Forum.http://hdl.handle.net/11449/170552This paper shows the influence of back gate bias on transistor efficiency of nMOS SOI Ω-gate nanowire, for different width and channel length. Threshold voltage and subthreshold swing present a higher variation with the back gate bias variation in wider devices. Long channel devices present better efficiency due to the better subthreshold swing, the same reason for the narrow devices have a better efficiency. Wider devices have a higher variation in efficiency when the back gate is biased. The transistor efficiency increases when the back gate is negative biased due to the better electrostatic coupling between gate and channel.engBack gateNanowireOmega-GateSOITransistor EfficiencyTrabalho apresentado em evento10.1109/SBMicro.2017.8113021Acesso aberto2-s2.0-8504057254304969095954656960000-0002-0886-7798