A low-voltage triode-MOSFET four-quadrant multiplier with optimized current-efficiency - De Lima, J. A. [UNESP] (Institute of Electrical and Electronics Engineers (IEEE), 2001)
A low-voltage, low-power four-quadrant analog multiplier with optimized current-efficiency is presented. Its core corresponds to a pseudodifferential cascode, gain-boosting triode-transconductor. According to a low-voltage 1.2μm CMOS n-well process, operand differential-amplitudes are 1.0Vpp and 0.32Vpp for a 1.3V-supply. Common-mode voltages are properly chosen to maximize current-efficiency to 58%. Total quiescent dissipation is 260μW. A range of PSPICE simulation supports theoretical analysis. Excellent linearity is observed on dc characteristic. Assuming a ±0.5% mismatch on (W/L) and VTH THD at full-scale is 0.93% and 1.42%, for output frequencies of 1MHz and 10MHz, respectively.
Keywords: Computer simulation; Energy dissipation; Gain control; Linear integrated circuits; MOSFET devices; Numerical analysis; Transconductance; Triodes; Current efficiency; Multiplying circuits