Martino, JoaoMesquita, ViniciusMacambira, ChristianItocazu, VitorAlmeida, LucianoAgopian, Paula [UNESP]Simoen, EddyClaeys, Cor2018-12-112018-12-112017-07-312016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings, p. 785-788.http://hdl.handle.net/11449/170085In this work the Zero Temperature Coefficient (ZTC) is investigated experimentally using state-of-the-art industrial technologies like Ultra-Thin Body and Buried Oxide (UTBB) and triple-gate FinFETs (irradiated and/or strained devices), both fabricated on Silicon On Insulator (SOI) wafers. A simple analytical model to analyze the behavior of the gate-source voltage at the Zero Temperature Coefficient point (VZTC) is validated for these advanced devices. Although simple, the model predictions have shown good agreement with the experimental results and can be useful for low-power low-voltage analog circuit designers, where biasing at/near the ZTC point should result in low thermal drift of the circuit operation.785-788engTrabalho apresentado em evento10.1109/ICSICT.2016.7999041Acesso aberto2-s2.0-8502864314704969095954656960000-0002-0886-7798