Oliveira, Vlademir J. S. [UNESP]Oki, Nobuo [UNESP]2014-05-202014-05-202007-01-012007 International Conference on Design & Technology of Integrated Systems In Nanoscale Era. New York: IEEE, p. 52-55, 2007.http://hdl.handle.net/11449/9689An analog CMOS current multiplier building block for low voltage applications using an n-well process is presented. The multiplier equations are derived to proof its linear characteristic, and then a low voltage design is proposed. Post layout simulation in a 0.35 mu m AMS CMOS process and 1.5V supply voltage shows a THD of 0.84% at 10 MHz and a frequency response bandwidth of 140 MHz.52-55engTrabalho apresentado em evento10.1109/DTIS.2007.4449491WOS:000256296500010Acesso aberto1525717947689076