Martino, M. D.V.Martino, J. A.Agopian, P. G.D. [UNESP]Rooyackers, R.Simoen, E.Collaert, N.Claeys, C.2018-12-112018-12-112018-03-072017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, v. 2018-March, p. 1-3.http://hdl.handle.net/11449/171062The aim of this work is to study, for the first time, the behavior of differential pair circuits designed with Line TFETs and compare the suitability of this technology with alternatives such as FinFETs and Point TFETs. The first part highlights experimental characteristics of individual Line TFET transistors, which present similar transconductance and better output conductance when compared to FinFETs, while revealing better transconductance and worse output conductance in comparison to Point TFETs. Next, the experimental data for Line TFET differential pairs is presented for different bias conditions and dimensions. The last part compares the intrinsic voltage gain (Ad), the compliance voltage and susceptibility to channel length mismatch for the 3 technologies. It is explained that Line TFET presents the highest Ad, FinFETs provides a wider operation region and Point TFETs are the least susceptible to channel length variations.1-3engdifferential gainDifferential Pairdimensions mismatchFinFETLine TFETPoint TFETTrabalho apresentado em evento10.1109/S3S.2017.8308756Acesso restrito2-s2.0-8504775468804969095954656960000-0002-0886-7798