Analog design with Line-TFET device experimental data: From device to circuit level
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2020-05-01
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Gon alez Filho, Walter
Simoen, Eddy
Rooyackers, Rita
Claeys, Cor
Collaert, Nadine
Martino, Joao A
Agopian, Paula G D [UNESP]
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This work studies the use of line-tunnel field effect transistor (Line TFET) devices in analog applications. It presents the DC and small signal characteristics of these devices and compares them with other TFET topologies and with conventional MOSFET technology. The Line-TFET's saturation characteristics are also closely studied, through simulations and experimental characterization, revealing that point tunneling leakage from source to drain not only limits the bias voltage and the gate area but also makes the output conductance independent of the gate length. A common source stage is designed to illustrate and further explore this fact, making comparisons with conventional MOSFET technology. In order to obtain an amplifier with very high voltage gain, a two-stage operational transconductance amplifier is designed considering two different starting points: fixed transistor efficiency (gm/Ids) or fixed normalized current (Ids/W) in order to obtain similar conditions of performance for Line-TFET and MOSFET devices. It is revealed that the Line-TFET design always achieves much higher intrinsic voltage gain (of up to 115 dB) and is more suitable for low power, low frequency applications. Thus, a third design is performed with Line-TFET devices by using gate lengths of 100 nm, achieving 71 dB of open loop voltage gain and 18 nW of power dissipation, which may be suitable for applications such as bio-signal acquisition.
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Semiconductor Science and Technology, v. 35, n. 5, 2020.