Energy-aware Scheduling in Transactional Memory Systems
| dc.contributor.author | Marques Junior, Ademir [UNESP] | |
| dc.contributor.author | Baldassin, Alexandro [UNESP] | |
| dc.contributor.author | IEEE | |
| dc.contributor.institution | Universidade Estadual Paulista (Unesp) | |
| dc.date.accessioned | 2018-11-26T15:37:52Z | |
| dc.date.available | 2018-11-26T15:37:52Z | |
| dc.date.issued | 2016-01-01 | |
| dc.description.abstract | Transaction scheduling is a relatively new technique for transactional memory systems responsible for deciding which transactions to run in a given moment. Current transactional schedulers are designed with performance in mind, leaving unattended other important metrics such as energy consumption. In order to address this important concern, this paper presents a novel heuristic, called Dynamic Serializer (DS), for scheduling transactions with the aim of reducing energy consumption and improving the energy-delay product (EDP) of transactional applications. DS serializes the execution by choosing either a spinlock or mutex according to a dynamic profile based on abort rates. The idea is to use a spinlock when a transaction is likely to succeed in the near future, since spinning while waiting for the lock is faster than blocking as in the case of a mutex. On the other hand, a mutex is used in case transactions need to wait a long time before resuming because in this case energy can be saved by blocking a thread and enabling the processor Dynamic Voltage and Frequency Scaling (DVFS) to act. DS exploits this tradeoff to improve the EDP of transactional programs. Experimental results with an Intel Core i7 with 8 logical threads and the STAMP benchmark show an EDP improvement of up to 17% and an average of 4.9% compared to LUTS-Dynamic, a state-of-the-art scheduling heuristic for transactional systems. | en |
| dc.description.affiliation | Univ Estadual Paulista, UNESP, Rio Claro, Brazil | |
| dc.description.affiliationUnesp | Univ Estadual Paulista, UNESP, Rio Claro, Brazil | |
| dc.description.sponsorship | Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) | |
| dc.description.sponsorship | Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) | |
| dc.description.sponsorshipId | FAPESP: 2011/19373-6 | |
| dc.description.sponsorshipId | CNPq: 446160/2014-8 | |
| dc.format.extent | 6 | |
| dc.identifier.citation | 2016 29th Symposium On Integrated Circuits And Systems Design (sbcci). New York: Ieee, 6 p., 2016. | |
| dc.identifier.uri | http://hdl.handle.net/11449/159306 | |
| dc.identifier.wos | WOS:000392290600026 | |
| dc.language.iso | eng | |
| dc.publisher | Ieee | |
| dc.relation.ispartof | 2016 29th Symposium On Integrated Circuits And Systems Design (sbcci) | |
| dc.rights.accessRights | Acesso aberto | |
| dc.source | Web of Science | |
| dc.title | Energy-aware Scheduling in Transactional Memory Systems | en |
| dc.type | Trabalho apresentado em evento | |
| dcterms.license | http://www.ieee.org/publications_standards/publications/rights/rights_policies.html | |
| dcterms.rightsHolder | Ieee | |
| unesp.author.lattes | 4738829911864396[2] | |
| unesp.author.orcid | 0000-0001-8824-3055[2] |