Impact of Gate Current on Tfet and Finfet Verilog-a Model

Abstract

This work presents the impact of gate current on modeling of pFinFET and pTunnel-FET (pTFET) transistors fabricated on the same SOI wafer. Both devices were measured at room temperature for a fin width/height of $20 ~\text{nm} / 65 ~\text{nm}$ and channel length of 150 nm. The impact of gate leakage current on modeling, performed using the Cadence Virtuoso software and the look-up table method, was evaluated by the comparison of models based only on drain current and models that consider all relevant currents. Since the drain current of TFET transistors is very low which has the same order of magnitude as the gate leakage current, it was observed that it is essential to consider the gate current when modeling this type of transistor, particularly in applications operating at low drain voltages. In contrast, pFinFET showed no significant influence from the gate current, allowing it to be safely neglected in the Verilog-A model.