PhTM*: uma implementação eficiente de transações em fases
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Data
2016-06-07
Autores
Carvalho, João Paulo Labegalini de [UNESP]
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Editor
Universidade Estadual Paulista (Unesp)
Resumo
As evidentes limitações em se explorar o aumento de frequência e otimização no nível de microarquitetura para obtenção de desempenho levaram a indústria de microprocessadores a buscar alternativas para suprir tal demanda. A solução encontrada foi construir arquiteturas com múltiplos fluxos de execução (multicore). No entanto, a utilização imediata do modelo paralelo exige que os programadores precisem explicitamente codificar as aplicações de forma a usar todos os núcleos, tarefa essa nada trivial e passível de erros que, muitas vezes, são difíceis de serem detectados. Um novo modelo de programação concorrente conhecido como memória transacional (Transactional Memory – TM) oferece abstrações para fácil codificação de aplicações e é capaz de explorar o paralelismo das arquiteturas multicore sem exigir conhecimentos da arquitetura por parte do programador. Porém, as implementações desse modelo, em software ou hardware, isoladamente apresentam problemas que limitam a escalabilidade das aplicações. Objetivando resolver tais problemas, foram propostos sistemas híbridos de transações em hardware e software para melhor exploração do paralelismo, denominado Memória Transacional Híbrida (Hybrid Transactional Memory – HyTM). A flexibilidade dos sitemas híbridos convencionais, mesmo permitindo executar transações em hardware e software simultaneamente, reduzem o desempenho de ambos seus componentes e tornam mais complexa a implementação da componente em software. Nesse sentido, este trabalho apresenta a primeira implementação eficiente (PhTM*) de um sistema de transações em fases, proposto como alternativa aos HyTMs convencionais. O PhTM* elimina a instrumentação das transações em hardware, necessária em outros HyTMs, e permite utilizar qualquer STM, sem nenhuma modificação, para executar as transações em software. A proposta é a primeira a utilizar o suporte transacioal em hardware disponível em um processador real (não-emulado), para executar as transações em hardware. Os resultados mostram que o PhTM* foi capaz de escolher o modo mais adequado para todas as aplicações do STAMP utilizadas. De fato, o PhTM* apresentou o melhor desempenho entre os sistemas transacionais avaliados e foi cerca de 12% melhor que o HyTM-NOrec, sistema híbrido considerado baseline na avaliação de novos HyTMs.
The limited performance gain due to micro-architectural optimizations and the modest increase in clock rate led the microprocessor industry to seek alternatives to single-core processors in order to keep up with the performance demand. The solution found was to build architectures with multiple execution flows (multicore). Nonetheless, the parallel model’s immediate adoption requires programmers to explicitly code applications in a way that all cores are used. Yet this task has proven to be non-trivial and prone to errors, which are generally hard to detect. A new concurrent programming model known as transactional memory (TM) brings abstractions that ease the synchronization burdens of parallel coding and enables programmers to better exploit the parallelism of multicore architectures without knowing their details. However, software and hardware implementations of the TM model have proven to be limited when adopted in isolation. Hybrid transactional systems (HyTM) are the proposed solution to these problems, allowing applications to benefit from multicore machines. The flexibility of conventional hybrid systems, even though allowing simultaneous execution of hardware and software transactions, decrease the performance of both hardware and software and increase the complexity of the software component. In this direction, this work presents the first eficient implementation (PhTM*) of phase-based transactional system, a viable alternative to conventional HyTMs. PhTM* removes the aditional instrumentation of hardware transactions, necessary in other HyTMs, and can use any STM library to execute software transactions. The proposal is the first to use hardware transactional support, available in a real (not emulated) processor, to run hardware transactions. The results show that PhTM* is capable of always choosing the best suited mode for all STAMP applications. In fact, PhTM* showed the best overall performance and was about 12% better then HyTM-NOrec, a de facto baseline in HyTM evaluation.
The limited performance gain due to micro-architectural optimizations and the modest increase in clock rate led the microprocessor industry to seek alternatives to single-core processors in order to keep up with the performance demand. The solution found was to build architectures with multiple execution flows (multicore). Nonetheless, the parallel model’s immediate adoption requires programmers to explicitly code applications in a way that all cores are used. Yet this task has proven to be non-trivial and prone to errors, which are generally hard to detect. A new concurrent programming model known as transactional memory (TM) brings abstractions that ease the synchronization burdens of parallel coding and enables programmers to better exploit the parallelism of multicore architectures without knowing their details. However, software and hardware implementations of the TM model have proven to be limited when adopted in isolation. Hybrid transactional systems (HyTM) are the proposed solution to these problems, allowing applications to benefit from multicore machines. The flexibility of conventional hybrid systems, even though allowing simultaneous execution of hardware and software transactions, decrease the performance of both hardware and software and increase the complexity of the software component. In this direction, this work presents the first eficient implementation (PhTM*) of phase-based transactional system, a viable alternative to conventional HyTMs. PhTM* removes the aditional instrumentation of hardware transactions, necessary in other HyTMs, and can use any STM library to execute software transactions. The proposal is the first to use hardware transactional support, available in a real (not emulated) processor, to run hardware transactions. The results show that PhTM* is capable of always choosing the best suited mode for all STAMP applications. In fact, PhTM* showed the best overall performance and was about 12% better then HyTM-NOrec, a de facto baseline in HyTM evaluation.
Descrição
Palavras-chave
Programação concorrente, Memória transacional, Sistemas híbridos, Fases do programa, Concurrent programming, Transactional memory, Hybrid systems, Program phase