Using multiple abstraction levels to speedup an MPSoC virtual platform simulator

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dc.contributor.authorMoreira, João
dc.contributor.authorKlein, Felipe
dc.contributor.authorBaldassin, Alexandro [UNESP]
dc.contributor.authorCentoducatte, Paulo
dc.contributor.authorAzevedo, Rodolfo
dc.contributor.authorRigo, Sandro
dc.contributor.institutionUniversidade Estadual de Campinas (UNICAMP)
dc.contributor.institutionUniversidade Estadual Paulista (Unesp)
dc.date.accessioned2014-05-27T11:25:57Z
dc.date.available2014-05-27T11:25:57Z
dc.date.issued2011-07-28
dc.description.abstractVirtual platforms are of paramount importance for design space exploration and their usage in early software development and verification is crucial. In particular, enabling accurate and fast simulation is specially useful, but such features are usually conflicting and tradeoffs have to be made. In this paper we describe how we integrated TLM communication mechanisms into a state-of-the-art, cycle-accurate, MPSoC simulation platform. More specifically, we show how we adapted ArchC fast functional instruction set simulators to the MPARM platform in order to achieve both fast simulation speed and accuracy. Our implementation led to a much faster hybrid platform, reaching speedups of up to 2.9 and 2.1x on average with negligible impact on power estimation accuracy (average 3.26% and 2.25% of standard deviation). © 2011 IEEE.en
dc.description.affiliationInstitute of Computing University of Campinas (UNICAMP)
dc.description.affiliationIGCE DEMAC UNESP
dc.description.affiliationUnespIGCE DEMAC UNESP
dc.format.extent99-105
dc.identifierhttp://dx.doi.org/10.1109/RSP.2011.5929982
dc.identifier.citationProceedings of the International Workshop on Rapid System Prototyping, p. 99-105.
dc.identifier.doi10.1109/RSP.2011.5929982
dc.identifier.issn1074-6005
dc.identifier.scopus2-s2.0-79960688876
dc.identifier.urihttp://hdl.handle.net/11449/72565
dc.language.isoeng
dc.relation.ispartofProceedings of the International Workshop on Rapid System Prototyping
dc.rights.accessRightsAcesso aberto
dc.sourceScopus
dc.subjectAbstraction level
dc.subjectCommunication mechanisms
dc.subjectCycle accurate
dc.subjectDesign space exploration
dc.subjectFast simulation
dc.subjectHybrid platform
dc.subjectInstruction set simulators
dc.subjectPower estimations
dc.subjectSimulation platform
dc.subjectStandard deviation
dc.subjectVirtual platform
dc.subjectEmbedded systems
dc.subjectMultiprocessing systems
dc.subjectSoftware design
dc.subjectSpace platforms
dc.subjectSpace research
dc.subjectSpecifications
dc.subjectVerification
dc.subjectComputer software
dc.titleUsing multiple abstraction levels to speedup an MPSoC virtual platform simulatoren
dc.typeTrabalho apresentado em evento
dcterms.licensehttp://www.ieee.org/publications_standards/publications/rights/rights_policies.html
unesp.author.lattes4738829911864396[3]
unesp.author.orcid0000-0001-8824-3055[3]
unesp.campusUniversidade Estadual Paulista (Unesp), Instituto de Geociências e Ciências Exatas, Rio Claropt

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Artigos - Estatistica, Matemática Aplicada e Computação - IGCE