A low-voltage low-sensitivity sinusoidal VCO for DPLL realizations

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dc.contributor.authorDe Lima, Jader A. [UNESP]
dc.contributor.authorAgostinho, Peterson R. [UNESP]
dc.contributor.institutionUniversidade Estadual Paulista (Unesp)
dc.date.accessioned2014-05-27T11:21:09Z
dc.date.available2014-05-27T11:21:09Z
dc.date.issued2004-09-07
dc.description.abstractA quasi-sinusoidal linearly tunable OTA-C VCO built with triode-region transconductors is presented. Oscillation upon power-on is ensured by RHP poles associated with gate-drain capacitances of OTA input devices. Since the OTA nonlinearity stabilizes the amplitude, the oscillation frequency f0 is first-order independent of VDD, making the VCO adequate to mixed-mode designs. A range of simulations attests the theoretical analysis. As part of a DPLL, the VCO was prototyped on a 0.8μm CMOS process, occupying an area of 0.15mm2. Nominal f0 is 1MHz, with K VCo=8.4KHz/mV. Measured sensitivity to VDD is below 2.17, while phase noise is -86dBc at 100-KHz offset. The feasibility of the VCO for higher frequencies is verified by a redesign based on a 0.35μm CMOS process and VDD=3.3V, with a linear frequency-span of l3.2MHz - 61.5MHz.en
dc.description.affiliationLab. of VLSI Des./Instrumentation Electrical Engineering Department Universidade Estadual Paulista, 12510-416 Guaratinguetá - SP
dc.description.affiliationUnespLab. of VLSI Des./Instrumentation Electrical Engineering Department Universidade Estadual Paulista, 12510-416 Guaratinguetá - SP
dc.identifierhttp://dx.doi.org/10.1109/ISCAS.2004.1328313
dc.identifier.citationProceedings - IEEE International Symposium on Circuits and Systems, v. 1.
dc.identifier.doi10.1109/ISCAS.2004.1328313
dc.identifier.issn0271-4310
dc.identifier.scopus2-s2.0-4344578485
dc.identifier.urihttp://hdl.handle.net/11449/67875
dc.identifier.wosWOS:000223122300198
dc.language.isoeng
dc.relation.ispartofProceedings - IEEE International Symposium on Circuits and Systems
dc.relation.ispartofsjr0,237
dc.rights.accessRightsAcesso aberto
dc.sourceScopus
dc.subjectCapacitance
dc.subjectCMOS integrated circuits
dc.subjectComputer simulation
dc.subjectElectric conductance
dc.subjectElectric potential
dc.subjectJitter
dc.subjectLogic design
dc.subjectMOSFET devices
dc.subjectSwitching
dc.subjectTransconductance
dc.subjectTransfer functions
dc.subjectOTA
dc.subjectPhase noise
dc.subjectRing oscillators
dc.subjectWaveforms
dc.subjectVariable frequency oscillators
dc.titleA low-voltage low-sensitivity sinusoidal VCO for DPLL realizationsen
dc.typeTrabalho apresentado em evento
dcterms.licensehttp://www.ieee.org/publications_standards/publications/rights/rights_policies.html
unesp.campusUniversidade Estadual Paulista (Unesp), Faculdade de Engenharia, Guaratinguetápt

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