Publicação: Analog Figures of Merit of Vertically Stacked Silicon Nanosheets nMOSFETs With Two Different Metal Gates for the Sub-7 nm Technology Node Operating at High Temperatures
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Ieee-inst Electrical Electronics Engineers Inc
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Resumo
The analysis of vertically stacked nanosheet (NS) n-type transistors with two different metal gate-stacks (with a total thickness of 7.5 and 4.7 nm) is presented in this work from room temperature to 200 degrees C. The focus in this work is on the classical analog figures of merit (FoM). In all NS devices, superior performance is observed that is confirmed by the subthreshold swing variation with temperature, which is very close to the theoretical thermal limit. The Al-based (n*) gate-stack NS n-channel NS field effect transistors (NSFETs) in general present higher transconductance, transistor efficiency, early voltage, and intrinsic voltage gain (A(V)) thanks to the better electrostatic coupling between the gates and the silicon NSs. An A(V) of about 47 dB (gate-stack (n*), L = 200 nm, 200 degrees C) is obtained. The low-frequency noise analysis demonstrates the presence of flicker noise dominated by carrier number fluctuations as the main type of noise and presents a low current noise power spectral density Sid of 10(-19) A(2)/Hz at a drain current of 1 mu A and a drain voltage of 50 mV for a frequency of 10 Hz.
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1/f noise, analog operation, low-frequency (LF) noise, MOSFET, nanosheets (NSs)
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Inglês
Como citar
Ieee Transactions On Electron Devices. Piscataway: Ieee-inst Electrical Electronics Engineers Inc, v. 68, n. 7, p. 3630-3635, 2021.
