Publicação: Operational Transconductance Amplifier Design with Gate- All-Around Nanosheet MOSFET using Experimental Lookup Table Approach
dc.contributor.author | Sousa, Julia C. S. | |
dc.contributor.author | Perina, Welder F. | |
dc.contributor.author | Simoen, Eddy | |
dc.contributor.author | Veloso, Anabela | |
dc.contributor.author | Martino, Joao A. | |
dc.contributor.author | Agopian, Paula G. D. [UNESP] | |
dc.contributor.author | IEEE | |
dc.contributor.institution | Universidade de São Paulo (USP) | |
dc.contributor.institution | IMEC | |
dc.contributor.institution | Universidade Estadual Paulista (UNESP) | |
dc.date.accessioned | 2022-11-30T13:38:23Z | |
dc.date.available | 2022-11-30T13:38:23Z | |
dc.date.issued | 2021-01-01 | |
dc.description.abstract | This paper presents the design of an Operational Transconductance Amplifier (OTA) with Gate-All-Around Nanosheet MOSFETs (GAA-NSH). The circuit simulation was performed using an experimental Lookup Table (LUT) approach. The experimental drain current and gate capacitance were extracted and used in a Verilog-A model in order to design the OTA for different transistor efficiency (gm/ID) values. The results present a compromise between power consumption (PC), voltage gain (Av) and the Gain-Bandwidth-Product (GBW). For gm/In of 8 V-1 an Av of 71.8 dB is obtained for a GBW of 361.3 MHz. These results were compared with other OTA designs using FinFET and TFET devices. The NSH OTA presents higher GBW, and considering the Av and PC, while NSH present better behavior than FinFETs, the behavior is worse than TFET OTA circuit for strong inversion operation. | en |
dc.description.affiliation | Univ Sao Paulo, LSI PSI USP, Sao Paulo, Brazil | |
dc.description.affiliation | IMEC, Leuven, Belgium | |
dc.description.affiliation | Sao Paulo State Univ, UNESP, Sao Joao Da Boa Vista, Brazil | |
dc.description.affiliationUnesp | Sao Paulo State Univ, UNESP, Sao Joao Da Boa Vista, Brazil | |
dc.description.sponsorship | Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) | |
dc.description.sponsorship | Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) | |
dc.format.extent | 4 | |
dc.identifier | http://dx.doi.org/10.1109/EuroSOI-ULIS53016.2021.9560689 | |
dc.identifier.citation | 2021 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (eurosoi-ulis). New York: Ieee, 4 p., 2021. | |
dc.identifier.doi | 10.1109/EuroSOI-ULIS53016.2021.9560689 | |
dc.identifier.issn | 2330-5738 | |
dc.identifier.uri | http://hdl.handle.net/11449/237554 | |
dc.identifier.wos | WOS:000790181800039 | |
dc.language.iso | eng | |
dc.publisher | Ieee | |
dc.relation.ispartof | 2021 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (eurosoi-ulis) | |
dc.source | Web of Science | |
dc.subject | Nanosheet (NSH) | |
dc.subject | Operational Transconductance Amplifier | |
dc.subject | Transistor Efficiency (g(m)/I-D) | |
dc.subject | Lookup Table | |
dc.subject | Analog Circuit Design | |
dc.title | Operational Transconductance Amplifier Design with Gate- All-Around Nanosheet MOSFET using Experimental Lookup Table Approach | en |
dc.type | Trabalho apresentado em evento | pt |
dcterms.license | http://www.ieee.org/publications_standards/publications/rights/rights_policies.html | |
dcterms.rightsHolder | Ieee | |
dspace.entity.type | Publication | |
unesp.campus | Universidade Estadual Paulista (UNESP), Faculdade de Engenharia, São João da Boa Vista | pt |