Logotipo do repositório
 

Publicação:
Operational Transconductance Amplifier Design with Gate- All-Around Nanosheet MOSFET using Experimental Lookup Table Approach

dc.contributor.authorSousa, Julia C. S.
dc.contributor.authorPerina, Welder F.
dc.contributor.authorSimoen, Eddy
dc.contributor.authorVeloso, Anabela
dc.contributor.authorMartino, Joao A.
dc.contributor.authorAgopian, Paula G. D. [UNESP]
dc.contributor.authorIEEE
dc.contributor.institutionUniversidade de São Paulo (USP)
dc.contributor.institutionIMEC
dc.contributor.institutionUniversidade Estadual Paulista (UNESP)
dc.date.accessioned2022-11-30T13:38:23Z
dc.date.available2022-11-30T13:38:23Z
dc.date.issued2021-01-01
dc.description.abstractThis paper presents the design of an Operational Transconductance Amplifier (OTA) with Gate-All-Around Nanosheet MOSFETs (GAA-NSH). The circuit simulation was performed using an experimental Lookup Table (LUT) approach. The experimental drain current and gate capacitance were extracted and used in a Verilog-A model in order to design the OTA for different transistor efficiency (gm/ID) values. The results present a compromise between power consumption (PC), voltage gain (Av) and the Gain-Bandwidth-Product (GBW). For gm/In of 8 V-1 an Av of 71.8 dB is obtained for a GBW of 361.3 MHz. These results were compared with other OTA designs using FinFET and TFET devices. The NSH OTA presents higher GBW, and considering the Av and PC, while NSH present better behavior than FinFETs, the behavior is worse than TFET OTA circuit for strong inversion operation.en
dc.description.affiliationUniv Sao Paulo, LSI PSI USP, Sao Paulo, Brazil
dc.description.affiliationIMEC, Leuven, Belgium
dc.description.affiliationSao Paulo State Univ, UNESP, Sao Joao Da Boa Vista, Brazil
dc.description.affiliationUnespSao Paulo State Univ, UNESP, Sao Joao Da Boa Vista, Brazil
dc.description.sponsorshipConselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)
dc.description.sponsorshipCoordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)
dc.format.extent4
dc.identifierhttp://dx.doi.org/10.1109/EuroSOI-ULIS53016.2021.9560689
dc.identifier.citation2021 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (eurosoi-ulis). New York: Ieee, 4 p., 2021.
dc.identifier.doi10.1109/EuroSOI-ULIS53016.2021.9560689
dc.identifier.issn2330-5738
dc.identifier.urihttp://hdl.handle.net/11449/237554
dc.identifier.wosWOS:000790181800039
dc.language.isoeng
dc.publisherIeee
dc.relation.ispartof2021 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (eurosoi-ulis)
dc.sourceWeb of Science
dc.subjectNanosheet (NSH)
dc.subjectOperational Transconductance Amplifier
dc.subjectTransistor Efficiency (g(m)/I-D)
dc.subjectLookup Table
dc.subjectAnalog Circuit Design
dc.titleOperational Transconductance Amplifier Design with Gate- All-Around Nanosheet MOSFET using Experimental Lookup Table Approachen
dc.typeTrabalho apresentado em eventopt
dcterms.licensehttp://www.ieee.org/publications_standards/publications/rights/rights_policies.html
dcterms.rightsHolderIeee
dspace.entity.typePublication
unesp.campusUniversidade Estadual Paulista (UNESP), Faculdade de Engenharia, São João da Boa Vistapt

Arquivos