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Optimization of the Dual-Technology Back-Enhanced Field Effect Transistor

dc.contributor.authorMori, C. A.B.
dc.contributor.authorAgopian, P. G.D. [UNESP]
dc.contributor.authorMartino, J. A.
dc.contributor.institutionUniversidade de São Paulo (USP)
dc.contributor.institutionUniversidade Estadual Paulista (Unesp)
dc.date.accessioned2021-06-25T10:26:24Z
dc.date.available2021-06-25T10:26:24Z
dc.date.issued2020-09-01
dc.description.abstractIn this paper we optimize the Dual-Technology Back-Enhanced SOI (DT BESOI) FETs varying the thickness of gate oxide, silicon film and buried oxide focusing on transfer characteristics. The DT BESOI optimization takes into account its behavior as both nMOS and pTunnel-FET device, which are obtained through the variation of positive and negative back biases. In the studied range, the optimized results were tox=lnm, tsi = 10nm and tBOX = 20nm. These DT BESOI results are compared with the conventional nMOS and pTFET devices.en
dc.description.affiliationLSI/PSI/USP University of Sao Paulo
dc.description.affiliationUNESP Sao Paulo State University
dc.description.affiliationUnespUNESP Sao Paulo State University
dc.identifierhttp://dx.doi.org/10.1109/EUROSOI-ULIS49407.2020.9365305
dc.identifier.citation2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020.
dc.identifier.doi10.1109/EUROSOI-ULIS49407.2020.9365305
dc.identifier.scopus2-s2.0-85102968209
dc.identifier.urihttp://hdl.handle.net/11449/206091
dc.language.isoeng
dc.relation.ispartof2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020
dc.sourceScopus
dc.subjectDual-Technology (DT)
dc.subjectSilicon-On-Insulator (SOI)
dc.subjectTunnel Field Effect Transistor (TFET)
dc.subjectUltra-Thin Body and Buried oxide (UTBB)
dc.titleOptimization of the Dual-Technology Back-Enhanced Field Effect Transistoren
dc.typeTrabalho apresentado em evento
dspace.entity.typePublication

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