Logo do repositório

Performance evaluation of Tunnel-FET basic amplifier circuits

dc.contributor.authorRangel, R. S.
dc.contributor.authorAgopian, P. G.D. [UNESP]
dc.contributor.authorMartino, J. A.
dc.contributor.institutionUniversidade de São Paulo (USP)
dc.contributor.institutionCI Brasil Program (CT-SP)
dc.contributor.institutionUniversidade Estadual Paulista (Unesp)
dc.date.accessioned2019-10-06T15:39:35Z
dc.date.available2019-10-06T15:39:35Z
dc.date.issued2019-03-14
dc.description.abstractThis work analyzes the performance of measured Tunneling Field-Effect Transistors (TFET) when applied to analog circuits. The method uses a look-up table based behavioral model, taking the experimental results from a fabricated silicon pTFET as input. The Verilog-A behavioral language is used to implement the TFET model, enabling the use with spice-like simulators along with passive and active elements, achieving bigger circuits than other implementations involving numerical multiphysics simulation of the device. The model is further incremented with device capacitances, and the response of analog circuits is considered. An Operational Transconductance Amplifier (OTA) is presented, showing near 130 dB open-loop gain and 18.9nW power consumption.en
dc.description.affiliationLSI/PSI/USP University of Sao Paulo
dc.description.affiliationCI Brasil Program (CT-SP)
dc.description.affiliationSao Paulo State University (UNESP) Sao Joao da Boa Vista
dc.description.affiliationUnespSao Paulo State University (UNESP) Sao Joao da Boa Vista
dc.format.extent21-24
dc.identifierhttp://dx.doi.org/10.1109/LASCAS.2019.8667587
dc.identifier.citation2019 IEEE 10th Latin American Symposium on Circuits and Systems, LASCAS 2019 - Proceedings, p. 21-24.
dc.identifier.doi10.1109/LASCAS.2019.8667587
dc.identifier.lattes0496909595465696
dc.identifier.orcid0000-0002-0886-7798
dc.identifier.scopus2-s2.0-85064163027
dc.identifier.urihttp://hdl.handle.net/11449/187543
dc.language.isoeng
dc.relation.ispartof2019 IEEE 10th Latin American Symposium on Circuits and Systems, LASCAS 2019 - Proceedings
dc.rights.accessRightsAcesso restritopt
dc.sourceScopus
dc.subjectCircuit Simulation
dc.subjectTFET
dc.subjectVerilog-A
dc.titlePerformance evaluation of Tunnel-FET basic amplifier circuitsen
dc.typeTrabalho apresentado em eventopt
dspace.entity.typePublication
relation.isOrgUnitOfPublication72ed3d55-d59c-4320-9eee-197fc0095136
relation.isOrgUnitOfPublication.latestForDiscovery72ed3d55-d59c-4320-9eee-197fc0095136
unesp.author.lattes0496909595465696[2]
unesp.author.orcid0000-0002-0886-7798[2]
unesp.campusUniversidade Estadual Paulista (UNESP), Faculdade de Engenharia, São João da Boa Vistapt

Arquivos