Publicação: A low-voltage low-sensitivity sinusoidal VCO for DPLL realizations
Carregando...
Data
Orientador
Coorientador
Pós-graduação
Curso de graduação
Título da Revista
ISSN da Revista
Título de Volume
Editor
Tipo
Trabalho apresentado em evento
Direito de acesso
Acesso aberto
Resumo
A quasi-sinusoidal linearly tunable OTA-C VCO built with triode-region transconductors is presented. Oscillation upon power-on is ensured by RHP poles associated with gate-drain capacitances of OTA input devices. Since the OTA nonlinearity stabilizes the amplitude, the oscillation frequency f0 is first-order independent of VDD, making the VCO adequate to mixed-mode designs. A range of simulations attests the theoretical analysis. As part of a DPLL, the VCO was prototyped on a 0.8μm CMOS process, occupying an area of 0.15mm2. Nominal f0 is 1MHz, with K VCo=8.4KHz/mV. Measured sensitivity to VDD is below 2.17, while phase noise is -86dBc at 100-KHz offset. The feasibility of the VCO for higher frequencies is verified by a redesign based on a 0.35μm CMOS process and VDD=3.3V, with a linear frequency-span of l3.2MHz - 61.5MHz.
Descrição
Palavras-chave
Capacitance, CMOS integrated circuits, Computer simulation, Electric conductance, Electric potential, Jitter, Logic design, MOSFET devices, Switching, Transconductance, Transfer functions, OTA, Phase noise, Ring oscillators, Waveforms, Variable frequency oscillators
Idioma
Inglês
Como citar
Proceedings - IEEE International Symposium on Circuits and Systems, v. 1.
