Output conductance of line-TFETs for different device parameters and its effect on basic analog circuits

This work addresses the impact of different device parameters on the analog characteristics of Line-Tunneling Field Effect Transistors (Line-TFETs). It was shown that in-creasing source-to-drain separation from 25 nm to 45 nm re-duces output conductance degradation for high drain voltages but increases the saturation voltage in about 400 mV due to the increase in the inner resistance. Variation of 4nm in the pocket thickness, a major cause of device variability, resulted in a 50-fold reduction of the drain current, but the output conductance reaches the same value in all cases for sufficiently high Vds. The variation of the main parameters responsible for device variability (pocket thickness and doping and gate-source alignment) is performed in order to analyze their impact on current mir-rors, revealing that gate-source overlap of 3 nm decreases the minimum output voltage from 820 mV to 300 mV, in comparison with no misalignment and improves the analog characteristics of the Line-TFET by preventing output conductance degradation for high drain voltages. Simulations compared to ex-perimental data show that the output conductance (gd) of Line-TFETs is practically independent of the gate length. Simulations reveal that this unique characteristic is due to source-to-drain tunneling, which defines the average value of gd on the saturation-like region and does not depend upon the gate length. The impact of this characteristic on the design of a com-mon-source stage is shown by comparing with a MOSFET de-sign. This example shows that the designer may choose whether to increase gm or gd in order to increase the circuit gain when using Line-TFETs, fundamentally differing from the MOSFET case.