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Optimal Synchronization of a Memristive Chaotic Circuit

dc.contributor.authorKountchou, Michaux
dc.contributor.authorLouodop, Patrick [UNESP]
dc.contributor.authorBowong, Samuel
dc.contributor.authorFotsin, Hilaire
dc.contributor.authorKurths, Jurgen
dc.contributor.institutionUniv Dschang
dc.contributor.institutionUniv Douala
dc.contributor.institutionPotsdam Inst Climate Impact Res PIK
dc.contributor.institutionInst Geol & Min Res
dc.contributor.institutionUniversidade Estadual Paulista (Unesp)
dc.contributor.institutionUMI 209 IRD
dc.contributor.institutionUPMC UMMISCO
dc.contributor.institutionLIRIMA
dc.contributor.institutionUniv Yaounde I
dc.contributor.institutionHumboldt Univ
dc.date.accessioned2018-11-26T16:48:18Z
dc.date.available2018-11-26T16:48:18Z
dc.date.issued2016-06-15
dc.description.abstractThis paper deals with the problem of optimal synchronization of two identical memristive chaotic systems. We first study some basic dynamical properties and behaviors of a memristor oscillator with a simple topology. An electronic circuit (analog simulator) is proposed to investigate the dynamical behavior of the system. An optimal synchronization strategy based on the controllability functions method with a mixed cost functional is investigated. A finite horizon is explicitly computed such that the chaos synchronization is achieved at an established time. Numerical simulations are presented to verify the effectiveness of the proposed synchronization strategy. Pspice analog circuit implementation of the complete master-slave-controller systems is also presented to show the feasibility of the proposed scheme.en
dc.description.affiliationUniv Dschang, Fac Sci, Dept Phys, Lab Elect & Signal Proc, POB 67, Dschang, Cameroon
dc.description.affiliationUniv Douala, Fac Sci, Dept Math & Comp Sci, Lab Appl Math, POB 24157, Douala, Cameroon
dc.description.affiliationPotsdam Inst Climate Impact Res PIK, Telegraphenberg A 31, D-14412 Potsdam, Germany
dc.description.affiliationInst Geol & Min Res, Nucl Technol Sect, POB 4110, Yaounde, Cameroon
dc.description.affiliationUniv Estadual Paulista, Inst Fis Teor, Rua Dr Bento Teobaldo Ferraz 271,Bloco 2, BR-01140070 Sao Paulo, Brazil
dc.description.affiliationUMI 209 IRD, Bondy, France
dc.description.affiliationUPMC UMMISCO, Bondy, France
dc.description.affiliationLIRIMA, Project Team GRIMCAPE, Yaounde, Cameroon
dc.description.affiliationUniv Yaounde I, African Ctr Excellence Informat & Commun Technol, Yaounde, Cameroon
dc.description.affiliationHumboldt Univ, Dept Phys, D-12489 Berlin, Germany
dc.description.affiliationUnespUniv Estadual Paulista, Inst Fis Teor, Rua Dr Bento Teobaldo Ferraz 271,Bloco 2, BR-01140070 Sao Paulo, Brazil
dc.description.sponsorshipFundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)
dc.description.sponsorshipAlexander von Humboldt Foundation, Germany
dc.description.sponsorshipIdFAPESP: 2014/13272-1
dc.format.extent18
dc.identifierhttp://dx.doi.org/10.1142/S0218127416500930
dc.identifier.citationInternational Journal Of Bifurcation And Chaos. Singapore: World Scientific Publ Co Pte Ltd, v. 26, n. 6, 18 p., 2016.
dc.identifier.doi10.1142/S0218127416500930
dc.identifier.issn0218-1274
dc.identifier.urihttp://hdl.handle.net/11449/161705
dc.identifier.wosWOS:000379354500004
dc.language.isoeng
dc.publisherWorld Scientific Publ Co Pte Ltd
dc.relation.ispartofInternational Journal Of Bifurcation And Chaos
dc.relation.ispartofsjr0,568
dc.rights.accessRightsAcesso restrito
dc.sourceWeb of Science
dc.subjectMemristor
dc.subjectmemristive devices
dc.subjectchaotic circuit
dc.subjectoptimal synchronization
dc.subjectPspice analog circuit implementation
dc.titleOptimal Synchronization of a Memristive Chaotic Circuiten
dc.typeArtigo
dcterms.rightsHolderWorld Scientific Publ Co Pte Ltd
dspace.entity.typePublication
unesp.campusUniversidade Estadual Paulista (UNESP), Instituto de Física Teórica (IFT), São Paulopt

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