Back gate influence on transistor efficiency of SOI nMOS Ω-gate nanowire down to 10nm width

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dc.contributor.authorItocazu, Vitor T.
dc.contributor.authorAlmeida, Luciano M.
dc.contributor.authorSonnenberg, Victor
dc.contributor.authorAgopian, Paula G. D. [UNESP]
dc.contributor.authorBarraud, Sylvain
dc.contributor.authorVinet, Maud
dc.contributor.authorFaynot, Olivier
dc.contributor.authorMartino, Joao A.
dc.contributor.institutionUniversidade de São Paulo (USP)
dc.contributor.institutionCEETEPS
dc.contributor.institutionUniversidade Estadual Paulista (Unesp)
dc.contributor.institutionMinatec Campus and University Grenoble Alpes
dc.date.accessioned2018-12-11T16:51:17Z
dc.date.available2018-12-11T16:51:17Z
dc.date.issued2017-11-15
dc.description.abstractThis paper shows the influence of back gate bias on transistor efficiency of nMOS SOI Ω-gate nanowire, for different width and channel length. Threshold voltage and subthreshold swing present a higher variation with the back gate bias variation in wider devices. Long channel devices present better efficiency due to the better subthreshold swing, the same reason for the narrow devices have a better efficiency. Wider devices have a higher variation in efficiency when the back gate is biased. The transistor efficiency increases when the back gate is negative biased due to the better electrostatic coupling between gate and channel.en
dc.description.affiliationLSI/PSI/USP University of Sao Paulo
dc.description.affiliationFATEC/SP and FATEC/OSASCO CEETEPS
dc.description.affiliationSao Paulo State University (UNESP)
dc.description.affiliationCEA LETI Minatec Campus and University Grenoble Alpes
dc.description.affiliationUnespSao Paulo State University (UNESP)
dc.identifierhttp://dx.doi.org/10.1109/SBMicro.2017.8113021
dc.identifier.citationSBMicro 2017 - 32nd Symposium on Microelectronics Technology and Devices: Chip on the Sands, co-located Symposia: 30th SBCCI - Circuits and Systems Design, 2nd INSCIT - Electronic Instrumentation, 7th WCAS - IC Design Cases and 17th SForum - Undergraduate-Student Forum.
dc.identifier.doi10.1109/SBMicro.2017.8113021
dc.identifier.lattes0496909595465696
dc.identifier.orcid0000-0002-0886-7798
dc.identifier.scopus2-s2.0-85040572543
dc.identifier.urihttp://hdl.handle.net/11449/170552
dc.language.isoeng
dc.relation.ispartofSBMicro 2017 - 32nd Symposium on Microelectronics Technology and Devices: Chip on the Sands, co-located Symposia: 30th SBCCI - Circuits and Systems Design, 2nd INSCIT - Electronic Instrumentation, 7th WCAS - IC Design Cases and 17th SForum - Undergraduate-Student Forum
dc.rights.accessRightsAcesso aberto
dc.sourceScopus
dc.subjectBack gate
dc.subjectNanowire
dc.subjectOmega-Gate
dc.subjectSOI
dc.subjectTransistor Efficiency
dc.titleBack gate influence on transistor efficiency of SOI nMOS Ω-gate nanowire down to 10nm widthen
dc.typeTrabalho apresentado em evento
unesp.author.lattes0496909595465696[4]
unesp.author.orcid0000-0002-0886-7798[4]

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