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Bit-parallel coprocessor for standard ECC-GF(2m) on FPGA

dc.contributor.authorDias, Maurício Araújo
dc.contributor.authorGouveia, Márcio Ricardo Alves [UNESP]
dc.contributor.authorOliveira, José Raimundo de
dc.contributor.authorMuñoz, Ignacio Bravo
dc.contributor.institutionUniversidade Estadual Paulista (Unesp)
dc.date.accessioned2015-04-27T11:56:00Z
dc.date.available2015-04-27T11:56:00Z
dc.date.issued2013
dc.description.abstractThis paper presents the design of a high-speed coprocessor for Elliptic Curve Cryptography over binary Galois Field (ECC- GF(2m)). The purpose of our coprocessor is to accelerate the scalar multiplication performed over elliptic curve points represented by affine coordinates in polynomial basis. Our method consists of using elliptic curve parameters over GF(2163) in accordance with international security requirements to implement a bit-parallel coprocessor on field-programmable gate-array (FPGA). Our coprocessor performs modular inversion by using a process based on the Stein's algorithm. Results are presented and compared to results of other related works. We conclude that our coprocessor is suitable for comparing with any other ECC-hardware proposal, since its speed is comparable to projective coordinate designs.en
dc.description.affiliationUniversidade Estadual Paulista Júlio de Mesquita Filho, Instituto de Biociências Letras e Ciências Exatas de São José do Rio Preto, Sao Jose do Rio Preto, Rua Cristóvão Colombo, 2265, Jardim Nazareth, CEP 15054-000, SP, Brasil
dc.description.affiliationUnespUniversidade Estadual Paulista Júlio de Mesquita Filho, Instituto de Biociências Letras e Ciências Exatas de São José do Rio Preto, Sao Jose do Rio Preto, Rua Cristóvão Colombo, 2265, Jardim Nazareth, CEP 15054-000, SP, Brasil
dc.description.affiliationUnespDepartment of Mathematics and Computation School of Science and Technology São Paulo State University (UNESP) Roberto Simonsen street, 305 Presidente Prudente, SP, 19060-900, BRAZIL
dc.description.affiliationUnespDepartment of Computer Engineering and Industrial Automation School of Electrical and Computer Engineering State University of Campinas (UNICAMP) Av. Albert Einstein, 400, Cid. Universitária Zeferino Vaz Distrito Barão Geraldo, Campinas, SP, 13083-852, BRAZIL
dc.description.affiliationUnespElectronics Department University Alcala DO-217. Polytechnic School Ctra. Madrid - Barcelona km. 33.6 Alcalá de Henares, Madrid, 28871, SPAIN
dc.format.extent241-262
dc.identifierhttp://www.diogenes.bg/ijam/contents/2013-26-2/10/
dc.identifier.citationInternational Journal of Applied Mathematics, v. 26, n. 1, p. 241-262, 2013.
dc.identifier.doi10.12732/ijam.v26i2.10
dc.identifier.issn1311-1728
dc.identifier.lattes7578944173575239
dc.identifier.lattes2740441033907310
dc.identifier.urihttp://hdl.handle.net/11449/122754
dc.language.isoeng
dc.relation.ispartofInternational Journal of Applied Mathematics
dc.rights.accessRightsAcesso aberto
dc.sourceCurrículo Lattes
dc.subjectelliptic curvesen
dc.subjectGF(2m)en
dc.subjectcryptographyen
dc.subjectbit-parallelen
dc.subjectcoprocessoren
dc.subjectFPGAen
dc.titleBit-parallel coprocessor for standard ECC-GF(2m) on FPGAen
dc.typeArtigo
unesp.author.lattes7578944173575239
unesp.author.lattes2740441033907310
unesp.campusUniversidade Estadual Paulista (Unesp), Instituto de Biociências, Letras e Ciências Exatas, São José do Rio Pretopt
unesp.departmentMatemática - IBILCEpt

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