The Case for Phase-Based Transactional Memory

Página do item simplificado
dc.contributor.authorDe Carvalho, Joao Paulo
dc.contributor.authorAraujo, Guido
dc.contributor.authorBaldassin, Alexandro
dc.contributor.institutionUniversidade Estadual de Campinas (UNICAMP)
dc.contributor.institutionUniversidade Estadual Paulista (Unesp)
dc.date.accessioned2018-12-11T16:54:47Z
dc.date.available2018-12-11T16:54:47Z
dc.date.issued2018-07-30
dc.description.abstractIn recent years, Hybrid TM (HyTM) has been proposed as a transactional memory approach that leverages on the advantages of both hardware (HTM) and software (STM) execution modes. HyTM assumes that concurrent transactions have very different phases and thus should run under different execution modes. Conversely, Phased Transactional Memory (PhTM) considers that concurrent transactions have similar phases, and thus all transactions could run under the same mode. In this paper we make the case for phase-based transactional systems using PhTM*, the first implementation of PhTM on modern HTM-ready processors. PhTM* novelty relies on avoiding unnecessary transitions to software mode. Experimental results using Broadwell's TSX reveal that, for the STAMP benchmark suite, PhTM* performs on average 1.68x better than PhTM, a previous phase-based TM, 2.08x better than HyTM-NOrec, a state-of-the-art HyTM, and 2.28x better than HyCO, the most recent hybrid system in the literature. We also show that STAMP applications do not exhibit hybrid behavior to justify the use of conventional hybrid systems, thus making PhTM* a better solution to those type of programs. Finally, we show for the first time that conventional hybrid systems do not perform better than phased-based system in a scenario with hybrid-behaved transactions.en
dc.description.affiliationInstitute of Computing, Universidade Estadual de Campinas, 28132 Campinas, São Paulo Brazil (e-mail: joao.carvalho@ic.unicamp.br)
dc.description.affiliationInstitute of Computing, Universidade Estadual de Campinas, 28132 Campinas, São Paulo Brazil (e-mail: guido@ic.unicamp.br)
dc.description.affiliationDepartamento de Computação, Matemática Aplicada e Estatástica, Universidade Estadual Paulista Julio de Mesquita Filho, 28108 Sao Paulo, SP Brazil (e-mail: alex@rc.unesp.br)
dc.identifierhttp://dx.doi.org/10.1109/TPDS.2018.2861712
dc.identifier.citationIEEE Transactions on Parallel and Distributed Systems.
dc.identifier.doi10.1109/TPDS.2018.2861712
dc.identifier.file2-s2.0-85050986775.pdf
dc.identifier.issn1045-9219
dc.identifier.scopus2-s2.0-85050986775
dc.identifier.urihttp://hdl.handle.net/11449/171297
dc.language.isoeng
dc.relation.ispartofIEEE Transactions on Parallel and Distributed Systems
dc.relation.ispartofsjr0,983
dc.rights.accessRightsAcesso aberto
dc.sourceScopus
dc.subjectBenchmark testing
dc.subjectHardware
dc.subjectPerformance evaluation
dc.subjectPerformance Evaluation
dc.subjectPhase-Based Execution
dc.subjectProgram processors
dc.subjectRuntime
dc.subjectSynchronization
dc.subjectTransactional Memory
dc.titleThe Case for Phase-Based Transactional Memoryen
dc.typeArtigo
unesp.author.lattes4738829911864396[3]
unesp.author.orcid0000-0001-8824-3055[3]

Arquivos

Pacote Original
Agora exibindo 1 - 1 de 1
Imagem de Miniatura
Nome:
2-s2.0-85050986775.pdf
Tamanho:
1.69 MB
Formato:
Adobe Portable Document Format
Descrição:
Baixar

Coleções

Artigos