The Case for Phase-Based Transactional Memory
dc.contributor.author | De Carvalho, Joao Paulo | |
dc.contributor.author | Araujo, Guido | |
dc.contributor.author | Baldassin, Alexandro | |
dc.contributor.institution | Universidade Estadual de Campinas (UNICAMP) | |
dc.contributor.institution | Universidade Estadual Paulista (Unesp) | |
dc.date.accessioned | 2018-12-11T16:54:47Z | |
dc.date.available | 2018-12-11T16:54:47Z | |
dc.date.issued | 2018-07-30 | |
dc.description.abstract | In recent years, Hybrid TM (HyTM) has been proposed as a transactional memory approach that leverages on the advantages of both hardware (HTM) and software (STM) execution modes. HyTM assumes that concurrent transactions have very different phases and thus should run under different execution modes. Conversely, Phased Transactional Memory (PhTM) considers that concurrent transactions have similar phases, and thus all transactions could run under the same mode. In this paper we make the case for phase-based transactional systems using PhTM*, the first implementation of PhTM on modern HTM-ready processors. PhTM* novelty relies on avoiding unnecessary transitions to software mode. Experimental results using Broadwell's TSX reveal that, for the STAMP benchmark suite, PhTM* performs on average 1.68x better than PhTM, a previous phase-based TM, 2.08x better than HyTM-NOrec, a state-of-the-art HyTM, and 2.28x better than HyCO, the most recent hybrid system in the literature. We also show that STAMP applications do not exhibit hybrid behavior to justify the use of conventional hybrid systems, thus making PhTM* a better solution to those type of programs. Finally, we show for the first time that conventional hybrid systems do not perform better than phased-based system in a scenario with hybrid-behaved transactions. | en |
dc.description.affiliation | Institute of Computing, Universidade Estadual de Campinas, 28132 Campinas, São Paulo Brazil (e-mail: joao.carvalho@ic.unicamp.br) | |
dc.description.affiliation | Institute of Computing, Universidade Estadual de Campinas, 28132 Campinas, São Paulo Brazil (e-mail: guido@ic.unicamp.br) | |
dc.description.affiliation | Departamento de Computação, Matemática Aplicada e Estatástica, Universidade Estadual Paulista Julio de Mesquita Filho, 28108 Sao Paulo, SP Brazil (e-mail: alex@rc.unesp.br) | |
dc.identifier | http://dx.doi.org/10.1109/TPDS.2018.2861712 | |
dc.identifier.citation | IEEE Transactions on Parallel and Distributed Systems. | |
dc.identifier.doi | 10.1109/TPDS.2018.2861712 | |
dc.identifier.file | 2-s2.0-85050986775.pdf | |
dc.identifier.issn | 1045-9219 | |
dc.identifier.scopus | 2-s2.0-85050986775 | |
dc.identifier.uri | http://hdl.handle.net/11449/171297 | |
dc.language.iso | eng | |
dc.relation.ispartof | IEEE Transactions on Parallel and Distributed Systems | |
dc.relation.ispartofsjr | 0,983 | |
dc.rights.accessRights | Acesso aberto | |
dc.source | Scopus | |
dc.subject | Benchmark testing | |
dc.subject | Hardware | |
dc.subject | Performance evaluation | |
dc.subject | Performance Evaluation | |
dc.subject | Phase-Based Execution | |
dc.subject | Program processors | |
dc.subject | Runtime | |
dc.subject | Synchronization | |
dc.subject | Transactional Memory | |
dc.title | The Case for Phase-Based Transactional Memory | en |
dc.type | Artigo | |
unesp.author.lattes | 4738829911864396[3] | |
unesp.author.orcid | 0000-0001-8824-3055[3] |
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