Subthreshold Region Analysis for UTBOX and UTBB SOI nMOSFETs with Different Channel Lengths and Silicon Thickness

Abstract

This paper presents an experimental analysis of the influence of the silicon thickness (t(si)) and the channel length (L) on the threshold voltage (V-T), subthreshold swing (SS), drain induced barrier lowering (DIBL), gate induced drain leakage (GIDL) and the ON-state over OFF-state current ratio (I-ON/I-OFF) on Ultra Thin Buried Oxide (UTBOX) and Ultra Thin Body and Buried oxide (UTBB) SOI nMOSFET devices. In order to complement this analysis, a simulation of the UTBB devices was performed. Devices with thinner silicon film present better control of short channel effects resulting in improved parameters such as SS(t(si)=50nm -> similar to 85-90 mV/dec; t(si)=20nm -> similar to 70-80 mV/dec), DIBL(t(si)=50nm -> similar to 130-150 mV/V; t(si)=20nm -> similar to 25-40 mV/V), GIDL and a reduction of the channel length influence on them. When comparing the UTBB devices without and with ground plane implantation (GP) it was noted that the GP did not affect the DIBL and GIDL parameters, but it increases V-T (similar to 0.25V without GP and similar to 0.45V with GP), degrades SS and improves I-ON/I-OFF (from similar to 10(5) without GP to similar to 10(8) with GP).