Experimental silicon tunnel-FET device model applied to design a Gm-C filter

dc.contributor.authorRangel, R. S.
dc.contributor.authorAgopian, P. G. D. [UNESP]
dc.contributor.authorMartino, J. A.
dc.contributor.institutionUniversidade de São Paulo (USP)
dc.contributor.institutionUniversidade Estadual Paulista (Unesp)
dc.contributor.institutionUniv Toronto
dc.date.accessioned2020-12-10T17:40:33Z
dc.date.available2020-12-10T17:40:33Z
dc.date.issued2020-09-01
dc.description.abstractThis work presents the design of a Gm-C filter using experimental data of a silicon tunneling field effect transistors (TFET) device. The application takes advantage of the low g(m)of a Si TFET device, resulting in an optimized low cutoff frequency filter, desired, for example, in biomedical applications. A look-up table model is used, with the experimental device data as input, which is reported to have an accurate response comparing to the measurements. The design of an operational amplifier circuit, the main part of a Gm-C filter, is presented, where around 100 dB voltage gain with two-stage topology is obtained. The filter showed a 100 Hz cutoff frequency response with 36 nW pole(-1)power consumption, which represents a significant improvement in comparison to recently reported designs using CMOS technology.en
dc.description.affiliationUniv Sao Paulo, LSI, PSI, Sao Paulo, Brazil
dc.description.affiliationSao Paulo State Univ, UNESP, Sao Joao Da Boa Vista, Brazil
dc.description.affiliationUniv Toronto, ECE, Toronto, ON, Canada
dc.description.affiliationUnespSao Paulo State Univ, UNESP, Sao Joao Da Boa Vista, Brazil
dc.description.sponsorshipConselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)
dc.format.extent7
dc.identifierhttp://dx.doi.org/10.1088/1361-6641/ab9ea8
dc.identifier.citationSemiconductor Science And Technology. Bristol: Iop Publishing Ltd, v. 35, n. 9, 7 p., 2020.
dc.identifier.doi10.1088/1361-6641/ab9ea8
dc.identifier.issn0268-1242
dc.identifier.urihttp://hdl.handle.net/11449/195614
dc.identifier.wosWOS:000561585200001
dc.language.isoeng
dc.publisherIop Publishing Ltd
dc.relation.ispartofSemiconductor Science And Technology
dc.sourceWeb of Science
dc.subjecttunnel-field effect transistor
dc.subjectanalog design
dc.subjectverilog-A
dc.titleExperimental silicon tunnel-FET device model applied to design a Gm-C filteren
dc.typeArtigo
dcterms.licensehttp://iopscience.iop.org/page/copyright
dcterms.rightsHolderIop Publishing Ltd

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