Towards a java bytecodes compiler for nios II soft-core processor

Página do item simplificado
dc.contributor.authorLima, Willian S. [UNESP]
dc.contributor.authorLobato, Renata S. [UNESP]
dc.contributor.authorManacero, Aleardo [UNESP]
dc.contributor.authorSpolon, Roberta [UNESP]
dc.contributor.institutionUniversidade Estadual Paulista (Unesp)
dc.date.accessioned2014-05-27T11:24:02Z
dc.date.available2014-05-27T11:24:02Z
dc.date.issued2009-11-19
dc.description.abstractReconfigurable computing is one of the most recent research topics in computer science. The Altera - Nios II soft-core processor can be included in a large set of reconfigurable architectures, especially because it is designed in software, allowing it to be configured according to the application. The recent growth in applications that demand reconfigurable computing made necessary the building of compilers that translate high level languages source codes into reconfigurable devices instruction sets. In this paper we present a compiler that takes as input the bytecodes generated by a Java front-end compiler and generates a set of instructions that attends to the Nios II processor instruction set rules. Our work shows how we process Java bytecodes to the intermediate code, in the Nios II instructions format, and build the control flow and the control dependence graphs. © 2009 IEEE.en
dc.description.affiliationDCCE UNESP São Paulo State University
dc.description.affiliationDC UNESP São Paulo State University
dc.description.affiliationUnespDCCE UNESP São Paulo State University
dc.description.affiliationUnespDC UNESP São Paulo State University
dc.format.extent104-109
dc.identifierhttp://dx.doi.org/10.1109/ISCC.2009.5202253
dc.identifier.citationProceedings - IEEE Symposium on Computers and Communications, p. 104-109.
dc.identifier.doi10.1109/ISCC.2009.5202253
dc.identifier.issn1530-1346
dc.identifier.lattes5568681374094860
dc.identifier.orcid0000-0001-8248-0826
dc.identifier.scopus2-s2.0-70449513605
dc.identifier.urihttp://hdl.handle.net/11449/71241
dc.identifier.wosWOS:000277119300017
dc.language.isoeng
dc.relation.ispartofProceedings - IEEE Symposium on Computers and Communications
dc.relation.ispartofsjr0,193
dc.rights.accessRightsAcesso aberto
dc.sourceScopus
dc.subjectBytecodes
dc.subjectControl flows
dc.subjectDependence graphs
dc.subjectInstruction set
dc.subjectJava bytecodes
dc.subjectNIOS II
dc.subjectReconfigurable architecture
dc.subjectReconfigurable computing
dc.subjectReconfigurable devices
dc.subjectResearch topics
dc.subjectSoft-core processors
dc.subjectSource codes
dc.subjectBuilding codes
dc.subjectComputer architecture
dc.subjectHigh level languages
dc.subjectProgram compilers
dc.titleTowards a java bytecodes compiler for nios II soft-core processoren
dc.typeTrabalho apresentado em evento
dcterms.licensehttp://www.ieee.org/publications_standards/publications/rights/rights_policies.html
unesp.author.lattes5320809446238024[3]
unesp.author.lattes5568681374094860[2]
unesp.author.orcid0000-0002-4581-7482[3]
unesp.author.orcid0000-0001-8248-0826[2]
unesp.campusUniversidade Estadual Paulista (Unesp), Instituto de Biociências Letras e Ciências Exatas, São José do Rio Pretopt
unesp.departmentCiências da Computação e Estatística - IBILCEpt

Arquivos

Coleções

São José do Rio Preto - IBILCE - Instituto de Biociências, Letras e Ciências Exatas