Analysis of Low-Dropout Voltage Regulator designed with Gate-All-Around nanosheet transistors
Carregando...
Arquivos
Fontes externas
Fontes externas
Data
Orientador
Coorientador
Pós-graduação
Curso de graduação
Título da Revista
ISSN da Revista
Título de Volume
Editor
Tipo
Trabalho apresentado em evento
Direito de acesso
Arquivos
Fontes externas
Fontes externas
Resumo
In this work the Low Dropout Voltage Regulator (LDO) was designed with gate-all-around nanosheet transistors (GAA-NSH). The simulation model was developed using Verilog-A code and the Look Up Table (LUT) was based on experimental data. The gm/ID of 10.5 V-1 was used for the differential pair in the LDO circuit, resulting in a dropout voltage of 340 mV through the power output transistor. The LDO designed with NSH transistors demonstrated promising results, such as an open-loop gain of 57 dB, a gain-bandwidth product of 52 MHz, and a power rejection rate of approximately -70 dB.
Descrição
Palavras-chave
GAA-NSH, LDO, LDO GAA-NSH, Low Dropout Voltage Regulator, Nanosheet device
Idioma
Inglês
Citação
2023 37th Symposium on Microelectronics Technology and Devices, SBMicro 2023.
