Publicação: Low voltage four-quadrant current multiplier: an improved topology for n-well CMOS process
dc.contributor.author | Oliveira, Vlademir J. S. [UNESP] | |
dc.contributor.author | Oki, Nobuo [UNESP] | |
dc.contributor.institution | Universidade Estadual Paulista (Unesp) | |
dc.date.accessioned | 2014-05-20T13:29:12Z | |
dc.date.available | 2014-05-20T13:29:12Z | |
dc.date.issued | 2010-10-01 | |
dc.description.abstract | An analog CMOS current multiplier building block for low voltage applications using an n-well process is presented. The multiplier equations are derived to proof its linear characteristic, and then a low voltage design is proposed. Post layout simulation in a 0.35 mu m AMS CMOS. process and 1.5 V supply voltage shows a THD of 0.84% at 10 MHz and a frequency response bandwidth of 140 MHz. | en |
dc.description.affiliation | Univ Estadual Paulista, Dept Engn Eletr, Ilha Solteira, Brazil | |
dc.description.affiliationUnesp | Univ Estadual Paulista, Dept Engn Eletr, Ilha Solteira, Brazil | |
dc.description.sponsorship | Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) | |
dc.description.sponsorship | Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) | |
dc.format.extent | 61-66 | |
dc.identifier | http://dx.doi.org/10.1007/s10470-009-9412-9 | |
dc.identifier.citation | Analog Integrated Circuits and Signal Processing. Dordrecht: Springer, v. 65, n. 1, p. 61-66, 2010. | |
dc.identifier.doi | 10.1007/s10470-009-9412-9 | |
dc.identifier.issn | 0925-1030 | |
dc.identifier.lattes | 1525717947689076 | |
dc.identifier.uri | http://hdl.handle.net/11449/9825 | |
dc.identifier.wos | WOS:000282012800006 | |
dc.language.iso | eng | |
dc.publisher | Springer | |
dc.relation.ispartof | Analog Integrated Circuits and Signal Processing | |
dc.relation.ispartofjcr | 0.800 | |
dc.relation.ispartofsjr | 0,211 | |
dc.rights.accessRights | Acesso restrito | |
dc.source | Web of Science | |
dc.subject | Current multiplier | en |
dc.subject | Low voltage | en |
dc.subject | Symmetrical | en |
dc.subject | Body effect | en |
dc.title | Low voltage four-quadrant current multiplier: an improved topology for n-well CMOS process | en |
dc.type | Resumo | |
dcterms.license | http://www.springer.com/open+access/authors+rights?SGWID=0-176704-12-683201-0 | |
dcterms.rightsHolder | Springer | |
dspace.entity.type | Publication | |
unesp.author.lattes | 1525717947689076 | |
unesp.campus | Universidade Estadual Paulista (UNESP), Faculdade de Engenharia, Ilha Solteira | pt |
unesp.department | Engenharia Elétrica - FEIS | pt |
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