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CNOT gate optimizations via qubit permutations for IBM's quantum architectures

dc.contributor.authorDe Almeida, Alexandre A.A. [UNESP]
dc.contributor.authorDueck, Gerhard W.
dc.contributor.authorDa Silva, Alexandre C.R. [UNESP]
dc.contributor.institutionUniversidade Estadual Paulista (Unesp)
dc.contributor.institutionUniversity of New Brunswick
dc.date.accessioned2019-10-06T15:53:36Z
dc.date.available2019-10-06T15:53:36Z
dc.date.issued2019-01-01
dc.description.abstractIBM offers a number of quantum processors on which scientist can perform experiments. All single qubit gates from the Clifford+T gate library are implemented, but only a subset of the possible CNOT are provided. It is well known that the functionally of the missing gates can be obtained with a sequence of gates. The sequence of gates is based on SWAP gates. Up to seven elementary gates are required to implement a SWAP gate. In this paper we show how the same effect can be achieved with fewer gates. Then, we propose an approach to find all the possible mappings for the missing CNOT gates. IBM's QX5 is used as target architecture. The proposed approach was compared to an algorithm that maps quantum circuits to IBM architectures. The benchmarks without optimizations techniques showed that our approach found circuits with up to 50% fewer gates and with up to 47% fewer levels. To optimize the benchmark circuits the quantum computing framework Qiskit was used. Comparing the optimized mapped circuits, our approach found circuits with up to 50% fewer gates and with up to 49% fewer levels.en
dc.description.affiliationDepartment of Electrical Engineering São Paulo State University (Unesp) School of Engineering
dc.description.affiliationFaculty of Computer Science University of New Brunswick
dc.description.affiliationUnespDepartment of Electrical Engineering São Paulo State University (Unesp) School of Engineering
dc.description.sponsorshipConselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)
dc.description.sponsorshipCoordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)
dc.description.sponsorshipNatural Sciences and Engineering Research Council of Canada
dc.description.sponsorshipUniversidade Estadual Paulista
dc.description.sponsorshipIdCNPq: 309193/2015-0
dc.description.sponsorshipIdCAPES: 88881.189547/2018- 01
dc.format.extent182-192
dc.identifierhttp://dx.doi.org/10.1166/jolpe.2019.1599
dc.identifier.citationJournal of Low Power Electronics, v. 15, n. 2, p. 182-192, 2019.
dc.identifier.doi10.1166/jolpe.2019.1599
dc.identifier.issn1546-2005
dc.identifier.issn1546-1998
dc.identifier.scopus2-s2.0-85071028672
dc.identifier.urihttp://hdl.handle.net/11449/187991
dc.language.isoeng
dc.relation.ispartofJournal of Low Power Electronics
dc.rights.accessRightsAcesso aberto
dc.sourceScopus
dc.subjectIBM Quantum Processor
dc.subjectMapping Algorithm
dc.subjectQuantum Circuit
dc.titleCNOT gate optimizations via qubit permutations for IBM's quantum architecturesen
dc.typeTrabalho apresentado em evento
dspace.entity.typePublication
unesp.author.lattes7360563327585400[3]
unesp.author.orcid0000-0003-3646-7801[3]

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