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Publicação:
Operational Transconductance Amplifier Designed with SiGe-source Nanowire Tunnel-FET using Experimental Lookup Table Model

dc.contributor.authorNogueira, Alexandro De M.
dc.contributor.authorAgopian, Paula G. D. [UNESP]
dc.contributor.authorSimoen, Eddy
dc.contributor.authorRooyackers, Rita
dc.contributor.authorClaeys, Cor
dc.contributor.authorCollaert, Nadine
dc.contributor.authorMartino, Joao A.
dc.contributor.institutionUniversidade de São Paulo (USP)
dc.contributor.institutionUniversidade Estadual Paulista (Unesp)
dc.contributor.institutionImec
dc.contributor.institutionClaRoo
dc.contributor.institutionE.E. Dept
dc.date.accessioned2021-06-25T10:26:25Z
dc.date.available2021-06-25T10:26:25Z
dc.date.issued2020-09-01
dc.description.abstractAn Operational Transconductance Amplifier (OTA) circuit designed with SiGe-source nanowire Tunnel-FETs is presented for the first time. The results are compared with Si nanowire TFET and with Si nanowire MOSFET designs. The transistors were modeled using experimental data in order to obtain a lookup table and the Verilog-A language for the circuit simulation. It was observed that there is a trade-off between the open loop gain (AV0) and the gain-bandwidth product (GBW) of these circuits. The Si-nanowire MOSFET OTA presents the lowest AV0 but the best GBW, while the Si nanowire TFET OTA presents the highest gain but the lowest GBW. The SiGe-source nanowire TFET OTA studied in this paper achieves a better compromise, which is, a better open loop gain (88 dB) than the Si-nanowire MOSFET circuit and a better gain-bandwidth product (718 kHz) than the Si nanowire TFET OTA.en
dc.description.affiliationLSI/PSI/USP University of Sao Paulo
dc.description.affiliationUNESP Sao Paulo State University
dc.description.affiliationImec
dc.description.affiliationClaRoo
dc.description.affiliationKU Leuven E.E. Dept
dc.description.affiliationUnespUNESP Sao Paulo State University
dc.identifierhttp://dx.doi.org/10.1109/EUROSOI-ULIS49407.2020.9365287
dc.identifier.citation2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020.
dc.identifier.doi10.1109/EUROSOI-ULIS49407.2020.9365287
dc.identifier.scopus2-s2.0-85102973828
dc.identifier.urihttp://hdl.handle.net/11449/206093
dc.language.isoeng
dc.relation.ispartof2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020
dc.sourceScopus
dc.subjectanalog circuits
dc.subjectlookup table
dc.subjectnanowire
dc.subjectOTA
dc.subjectSiGe
dc.subjectTunnel-FET
dc.titleOperational Transconductance Amplifier Designed with SiGe-source Nanowire Tunnel-FET using Experimental Lookup Table Modelen
dc.typeTrabalho apresentado em evento
dspace.entity.typePublication

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