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Application of UTBBBE SOI tunnel-FET as a dual-technology transistor

dc.contributor.authorCarlos Mori, A. B.
dc.contributor.authorPaula Agopian, G. D. [UNESP]
dc.contributor.authorMartino, Joao A.
dc.contributor.institutionUniversidade de São Paulo (USP)
dc.contributor.institutionUniversidade Estadual Paulista (Unesp)
dc.date.accessioned2020-12-12T01:09:52Z
dc.date.available2020-12-12T01:09:52Z
dc.date.issued2019-08-01
dc.description.abstractIn this work we propose for the first time the use of the recently introduced UTBBBE SOI TFET (Ultra-Thin Body and Box Back Enhanced Silicon-On-Insulator Tunnel-FET) operating as a MOSFET device only by changing its bias condition. The principle is based on the carrier type generated by the back gate electric field. For negative back gate and drain biases applied in the device studied in this work, it works like a pTFET, while for positive ones it operates as an nMOS. TCAD device simulation was used for the proof of concept.en
dc.description.affiliationUniversity of Sao Paulo LSI/PSI/USP
dc.description.affiliationUNESP Sao Paulo State University
dc.description.affiliationUnespUNESP Sao Paulo State University
dc.identifierhttp://dx.doi.org/10.1109/SBMicro.2019.8919316
dc.identifier.citationSBMicro 2019 - 34th Symposium on Microelectronics Technology and Devices.
dc.identifier.doi10.1109/SBMicro.2019.8919316
dc.identifier.scopus2-s2.0-85077182307
dc.identifier.urihttp://hdl.handle.net/11449/198329
dc.language.isoeng
dc.relation.ispartofSBMicro 2019 - 34th Symposium on Microelectronics Technology and Devices
dc.sourceScopus
dc.subjectdual technology transistor
dc.subjectMOSFET
dc.subjectReconfigurable transistor
dc.subjectSilicon-On-Insulator (SOI)
dc.subjectTunnel-FET
dc.titleApplication of UTBBBE SOI tunnel-FET as a dual-technology transistoren
dc.typeTrabalho apresentado em evento
dspace.entity.typePublication

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