Analysis of zero-temperature coefficient behavior on vertically stacked double nanosheet nMOS devices

Abstract

This work presents an experimental study of the zero-temperature coefficient (ZTC) bias point of vertically stacked gate-all-around (GAA) double nanosheet nMOS devices (GAA-NS) for different dimensions, operating in linear and saturation regions. The experimental data is also compared to a simple analytical ZTC model in order to better understand which electrical parameters impact the ZTC behavior. The variation of the threshold voltage with the temperature (ΔVTH/ΔT) and temperature transconductance degradation factor (c) are the two important aspects that most impact the gate to source voltage at ZTC (VZTC). Although the ZTC behavior of the GAA-NS nMOS devices studied in this paper is well described by the simple analytical ZTC model in linear region, at high drain bias, factors such as series resistance and carrier saturation velocity play a significant influence in the ZTC performance of GAA-NS nMOS devices examined in this study.