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Performance Perspective of Gate-All-Around Double Nanosheet CMOS Beyond High-Speed Logic Applications

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dc.contributor.authorSimoen, Eddy
dc.contributor.authorCoelho, Carlos H. S. [UNESP]
dc.contributor.authorda Silva, Vanessa C. P.
dc.contributor.authorMartino, Joao A.
dc.contributor.authorAgopian, Paula G. D. [UNESP]
dc.contributor.authorOliveira, Alberto
dc.contributor.authorCretu, Bogdan
dc.contributor.authorVeloso, Anabela
dc.contributor.institutionGhent University
dc.contributor.institutionUniversidade Estadual Paulista (UNESP)
dc.contributor.institutionUniversidade de São Paulo (USP)
dc.contributor.institutionFederal Technological University of Parana
dc.contributor.institutionGREYC
dc.contributor.institutionImec
dc.date.accessioned2023-07-29T12:44:37Z
dc.date.available2023-07-29T12:44:37Z
dc.date.issued2022-10-19
dc.description.abstractIn this review paper, the performance characteristics of Gate-All-Around (GAA) double nanosheet (NS) MOSFETs are described over a broad temperature range, from 78 K to 473 K (200oC). Emphasis is on the analog operation, showing good potential. Besides the transistor length, the impact of the metal gate Effective Work Function and the vertical distance between the nanosheets has been studied. Among oth-ers, a clear Zero Temperature Coefficient (ZTC) gate voltage has been observed that can be modeled by considering the shift with temperature of the threshold voltage and the maximum transconductance. A trade-off has been noticed between the transistor efficiency and the unit gain frequency, whereby the optimal operation point occurs in strong inversion regime. The feasibility of designing simple analog circuits has also been demonstrated. Finally, a detailed investigation of the low-fre-quency noise behavior yields good values for the flicker noise Power Spectral Density in comparison with other technology nodes.en
dc.description.affiliationDepart Solid State Sciences Ghent University
dc.description.affiliationUNESP Sao Paulo State University
dc.description.affiliationLSI/PSI/USP University of Sao Paulo
dc.description.affiliationUTFPR Federal Technological University of Parana
dc.description.affiliationUNICAEN ENSICAEN CNRS GREYC
dc.description.affiliationUPM Imec
dc.description.affiliationUnespUNESP Sao Paulo State University
dc.identifierhttp://dx.doi.org/10.29292/jics.v17i2.617
dc.identifier.citationJournal of Integrated Circuits and Systems, v. 17, n. 2, 2022.
dc.identifier.doi10.29292/jics.v17i2.617
dc.identifier.issn1872-0234
dc.identifier.issn1807-1953
dc.identifier.scopus2-s2.0-85145282457
dc.identifier.urihttp://hdl.handle.net/11449/246571
dc.language.isoeng
dc.relation.ispartofJournal of Integrated Circuits and Systems
dc.sourceScopus
dc.subjectanalog performance
dc.subjectcryogenic temperatures
dc.subjectGAA CMOS
dc.subjectlow-frequency noise
dc.titlePerformance Perspective of Gate-All-Around Double Nanosheet CMOS Beyond High-Speed Logic Applicationsen
dc.typeArtigo
dspace.entity.typePublication

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