Publicação: Interface charges influence on the subthreshold region from triple gate SOI FinFET to Ω-gate nanowire devices
dc.contributor.author | Silva, V. C.P. | |
dc.contributor.author | Martino, J. A. | |
dc.contributor.author | Agopian, P. G.D. [UNESP] | |
dc.contributor.institution | Universidade de São Paulo (USP) | |
dc.contributor.institution | Universidade Estadual Paulista (Unesp) | |
dc.date.accessioned | 2019-10-06T15:25:57Z | |
dc.date.available | 2019-10-06T15:25:57Z | |
dc.date.issued | 2018-10-26 | |
dc.description.abstract | In this paper, the influence of interface charges (fixed charges and interface traps) on the subthreshold region was analyzed focusing on the fin height. This influence was analyzed from Triple gate SOI FinFETs (devices with a high silicon height-hfin) to Ω-Gate Nanowires (with a small hfin). The results shows that as the fin height becomes smaller, the influence of interface charges is reduced due to the better electrostatic coupling. When the fin height becomes small enough, the interface charges did not influence both subthreshold swing and threshold voltage, even for wide devices, thanks to the supercoupling. | en |
dc.description.affiliation | LSI/PSI/USP University of Sao Paulo | |
dc.description.affiliation | Sao Paulo State University (UNESP) | |
dc.description.affiliationUnesp | Sao Paulo State University (UNESP) | |
dc.identifier | http://dx.doi.org/10.1109/SBMicro.2018.8511570 | |
dc.identifier.citation | 33rd Symposium on Microelectronics Technology and Devices, SBMicro 2018. | |
dc.identifier.doi | 10.1109/SBMicro.2018.8511570 | |
dc.identifier.lattes | 0496909595465696 | |
dc.identifier.orcid | 0000-0002-0886-7798 | |
dc.identifier.scopus | 2-s2.0-85057390341 | |
dc.identifier.uri | http://hdl.handle.net/11449/187114 | |
dc.language.iso | eng | |
dc.relation.ispartof | 33rd Symposium on Microelectronics Technology and Devices, SBMicro 2018 | |
dc.rights.accessRights | Acesso restrito | |
dc.source | Scopus | |
dc.title | Interface charges influence on the subthreshold region from triple gate SOI FinFET to Ω-gate nanowire devices | en |
dc.type | Trabalho apresentado em evento | |
dspace.entity.type | Publication | |
unesp.author.lattes | 0496909595465696[3] | |
unesp.author.orcid | 0000-0002-0886-7798[3] |